Implementation of Taguchi Method in Improving the Logic Gates Performance based on Carbon Nanotube Field Effect Transistor Technology

Abstract

The International Roadmap for Device and Systems (IRDS) 2022 has emphasized the potential of CNTFETs to replace CMOS technology. Therefore, the substitution of silicon with carbon nanotubes (CNTs) has the potential to open new possibilities for the semiconductor industry, due to their compact size and superior electrical properties. Thus, this project utilized Cadence Virtuoso software to develop an optimized CNTFET design using Taguchi method. In this design, the Taguchi method was implemented to determine the best combination of design parameter and material for optimum CNTFET performance. The design parameter and material that had been chosen were the diameter of carbon nanotube, dielectric material and oxide thickness. The optimized CNTFET model is implemented in circuit study to analyse the propagation delay and power consumption. Five circuits had been designed from the optimized CNTFET which are the inverter, AND, OR, NAND and NOR circuit. The Taguchi Optimization method resulted in significant reductions in the power- delay product (PDP) for all circuits examined, ranging from 7.9954% for the AND circuit to an exceptional 99.9622% for the inverter circuit. These findings highlight the potential for improved power efficiency and faster circuit operation when utilizing the Taguchi Optimization approach.