Integrated Injection Logic Research Articles

ИНЖЕКЦИОННО-ПОЛЕВАЯ СТРУКТУРА, ВЫПОЛНЕННАЯ ДВОЙНОЙ ДИФФУЗИЕЙ ПРИМЕСЕЙ

In the 80s of the last century, integrated injection logic (I2L) was widely used as an elementbase. Somewhat later, in the development of I2L, injection-field logic (IPL) appeared for the constructionof VLSI. Both element bases are close in the degree of integration on a chip. An increase inthe degree of integration into VLSI can be achieved using self-displacement of regions, in which theintroduction of impurities of different types is carried out using a single boundary of the maskingmaterial. In this paper, this principle is used to create a vertical channel of a key field-effect transistorof IPL logic. In a p-type epitaxial film deposited on an n+-type substrate, an n-type region with adepth greater than the thickness of the epitaxial film is sequentially created first, and then impuritydiffusion is performed in the same window with the creation of a region p-type. The gap betweenthese n-type regions is the channel of the field-effect transistor being formed. Next, a shallow n+-typeregion is created that overlaps the channel, which is the drain region of a key field-effect transistorwith a vertical channel, the p-type diffusion region is a gate, and the uniformly alloyed region of theepitaxial film performs the function of an injector. Branching along the outlet in this IPL structure isprovided by placing several drains along the perimeter of the channel. Due to this geometry, thestructure has a greater reproducibility of parameters compared to the basic design of the IPL. Topologicalvariants of the implementation of the IPL cell and schemes based on it are considered:schemes 6 OR-NOT and Dt-trigger. The proposed design and technological version of the IPL cellcan be recommended for creating VLSI of a high degree of integration

ЛОГИЧЕСКАЯ ЯЧЕЙКА ДЛЯ СБИС НА ОСНОВЕ ПОЛЕВЫХ ТРАНЗИСТОРОВ С P-N-ПЕРЕХОДАМИ

In the 80s of the last century, integrated injection logic (I2L) was widely used as an elementbase. Somewhat later, injection-field logic (IPL) appeared in the development of I2L capabilitiesfor building VLSI. Thanks to the use of a field-effect transistor as a key element of the inverter, inthis element basis it was possible to significantly reduce an important indicator for VLSI – powerconsumption - reaching the peak-watt range. An even greater reduction in power consumption canbe achieved by using two field-effect transistors in the inverter unit cell, which is proposed in thispaper. This element basis is proposed to be called field-field logic, or in the future P2L. To reducethe dimensions of the P2L cell, field-effect transistors, both key and load, are made with a verticalchannel. In addition, to ensure a positive supply voltage, an n-channel transistor is used as a keyone, and a p–channel transistor is used as a load one. Both transistors are normally closed, i.e.closed at zero gate voltage. Topological variants of P2L-cell execution from geometry with annulargates to geometry with linear gates proposed by the author earlier are considered. The topologicalnorms adopted in the consideration are the norms of 50 nm. The power consumption in thiselement basis is reduced by about two times compared to the IPL, due to the fact that the currentflows through the load transistors in the inverter chain through one inverter, as well as throughthe key ones. The technological process of manufacturing a P2L cell is considered, the profiles ofthe distribution of impurities in depth are calculated. The manufacturing process is designed takinginto account the fact that the load p-channel transistor must be made in an insulated pocketusing full dielectric insulation technology. The technological modes of manufacturing the P2L cellare given. The proposed design and technological variant of the P2L cell can be recommended forthe creation of VLSI with low power consumption.

A Perspective on SOI Symmetric Lateral Bipolar Transistors for Ultra-Low-Power Systems

The reasons why state-of-the-art vertical bipolar circuits dissipate very high power are explained. The recent advent of SOI symmetric lateral bipolar transistors invites us to rethink bipolar as a high-speed but low-power technology. Integrated Injection Logic ( $\text{I}^{2}\text{L}$ ) and complementary bipolar (analogous to CMOS) circuits in SOI lateral bipolar offer huge design windows for power versus performance tradeoff, suggesting the possibility of ultra-low-power systems with embedded high-speed cores. $\text{I}^{2}\text{L}$ SRAM cells could be more than twice as dense as CMOS SRAM cells. The SOI substrate offers a fourth device terminal that can be used to induce narrow-gap-base HBT-like I–V characteristics, which should further improve the power-performance of circuits in SOI lateral bipolar. Fin-structure devices enable significant improvement in ${f} _{\max }$ for RF and high-frequency applications. The process technology for SOI lateral bipolar is compatible with CMOS. The Si-OI version is definitely much less complex than CMOS.

Analysis of Si:Ge heterojunction integrated injection logic (I/sup 2/L) structures using a stored charge model

A quasi-two-dimensional stored charge model is developed as an aid to the optimization of SiGe integrated injection logic (I/sup 2/L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I/sup 2/L gate. Both the NpN switching transistor and the PNp load transistor are correctly modeled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I/sup 2/L and the Ge and doping concentrations varied to determine the important tradeoffs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NPN emitter layer. The inclusion of 16% Ge in the substrate-fed I/sup 2/L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable in SiGe I/sup 2/L even at a geometry of 3 /spl mu/m. The model is applied to a realistic, self-aligned structure and a delay of 34 ps is predicted. It is expected that this performance can be improved with a fully optimized, scaled structure.

Steady state and transient analysis of SFIIL

Steady state and transient analyses of substrate fed integrated injection logic (SFIIL) have been carried out using an injection model simply by merging all parallel diodes into a single composite diode. The upward gain of the NPN transistor, vertical PNP transistor gain and extrinsic delay of SFIIL devices have been computed for various device areas, junction depths and doping concentrations.

Predicted performance of high-speed integrated-injection logic using InGaAs/InP heterojunction bipolar transistors

By the use of analytical expressions and SPICE simulation, the switching performance of integrated injection logic (I/sup 2/L) using heterojunction bipolar transistors (HBTs) has been investigated. A proposed inverter configuration using InP/InGaAs HBTs which avoids saturation in the p-n-p injector has predicted propagation delays of 16 ps at only 3-mW power dissipation. Transient response analysis illustrates the importance of reducing parasitic resistances in the structure. Ring oscillator simulations indicate that switching speeds approaching those of emitter-coupled logic but with advantages in high density and low power are possible. >

Complementary AlGaAs/GaAs HBT I/sup 2/L (CHI/sup 2/L) technology

The monolithic integration of non-self-aligned AlGaAs/GaAs N-p-n and P-n-p HBTs with selective organometallic vapor-phase epitaxy (OMVPE) has been utilized to demonstrate a low-power high-speed integrated injection logic (I/sup 2/L) technology. Seventeen-stage ring oscillators with a logic swing of 0.7 V exhibited a delay of 65 ps per gate with power dissipation of 13 mW per gate for a speed-power product of 850 fJ. This value was in excellent agreement with SPICE simulations based on extracted device parameters which predicted a speed-power product of 840 fJ. Additional simulations predicated a 28-fJ speed-power product and more than a factor of 2 reduction in gate delay with improved epitaxial design and use of submicrometer emitters and self-aligned processing. >

370°Cまで動作するシリコンIILの試作

370°Cまで動作するシリコンIILの試作

Double heterojunction GaAlAs/GaAs I 2 L integrated circuits

The fabrication and DC characterisation of GaAlAs/GaAs double heterojunction bipolar transistors (DHBTs) grown by molecular beam epitaxy are described. This baseline process has been developed for the implementation of heterojunction integrated injection logic (HI/sup 2/L) integrated circuits. Results concerning an I/sup 2/L ring oscillator and a divide-by-two circuit are given.

The dual origins of a bipolar breakthrough (I/sup 2/L)

The author describes the independent discovery of integrated injection logic (I/sup 2/L) in the early 1970s by researchers at IBM in West Germany and at Philips in the Netherlands. He examines the factors that motivated the work and contrasts the viewpoints and working methods of the two teams, the Germans proceeding along a logical path to a solution that revealed itself to the Dutch team in a flash of intuition.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications

The CMOS nonthreshold logic (NTL) is derived from its bipolar counterpart, which is the fastest bipolar logic, and takes the NOR gate as its basic building gate. It is shown that by applying the nonthreshold principle to CMOS circuits speed performance can be highly improved, but with an increase of DC power consumption. From transient analyses the speed of CMOS NTL is found quite comparable to that of I/sup 2/L (integrated injection logic) or even ECL (emitter-coupled logic) and is about 20-60% better than that of conventional CMOS. Meanwhile, the power-delay product of CMOS NTL is smaller than those of I/sup 2/L and ECL and is nearly the same as that of conventional CMOS operated at high frequency. The nonthreshold principle is applied to the CMOS cascode structure to form the CMOS cascode nonthreshold logic (CNTL), in which there is a tradeoff between speed performance and power dissipation. It is shown from the design of full adders that the CMOS NTL is the fastest of all the static CMOS logic circuits. The speed of the CNTL circuit, although slower than that of the NTL circuit, is still higher than that of the DSL circuit, which is the fastest static circuit proposed so far. The CNTL circuit also has a smaller power-delay product than the DSL circuit. >

Modeling and performance of double heterojunction GaAlAs/GaAs integrated injection logic

Accurate modeling of double heterojunction GaAlAs/GaAs I 2 L has been carried out using a hybrid device model corresponding to the real structure, which includes the effects of parasitic lateral diodes and extrinsic base resistance. The charge-control relations are given in terms of physically meaningful device parameters and are applicable at all current levels. The results of dynamic simulation are used to analyze the influence of technological parameters and to discuss optimization criteria. The theoretical analysis indicates that a structure designed with 1 μm design rules and a fan-out of one should present a limit propagation time in the order of 100 ps (at a power consumption of 100 μW) and a factor of merit about 2 fJ at 1 μW.

The development of heterojunction integrated injection logic

The development of heterojunction integrated injection logic (HI/sup 2/L) since 1982 is described. The baseline process that uses AlGaAs/GaAs emitter-down HBTs (heterojunction bipolar transistors) as the switching element is presented. Two sets of design rules, one using a 7.0- mu m collector and 8.0- mu m metal pitch and another using a 5.0- mu m collector and 5.0- mu m metal pitch, have been developed for the pilot line circuit fabrication. Typical propagation delays obtained for a fan-out=4 HI/sup 2/L gate using the 7.0- and 5.0- mu m collector processes are 250 and 150 ps, respectively, at a power dissipation of 5 mW per gate. LSI and VLSI circuits as complex as 4 K-gate arrays and 32-bit MIPS microprocessors have been fabricated successfully using the HI/sup 2/L technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Steady state analysis of integrated injection logic

The current components occurring in the bulk of the conventional l2L device have been found solving the continuity equation incorporating the effects of heavy doping on the bandgap lowering, doping dependent mobility and time constants. The current gains of the forward and inverse operated pnp transistor and the upward operated npn transistor are found and compared with the available experimental results. The effect of various process parameters on the current gains has been studied. The current gains for the Substrate Fed Logic are also found. The theoretical results of the present analysis are found to be in close agreement with the experimental results.

Buried injector logic, a vertical IIL using deep ion implantation

A vertically integrated alternative for integrated injection logic has been realized, named buried injector logic (BIL). 1 MeV ion implantations are used to create buried layers. The vertical pnp and npn transistors have thin base regions and exhibit a limited charge accumulation if a gate is saturated. d.c. and dynamic analysis of BIL-gate behaviour are given. A minimum gate delay of well below 1 ns is projected if collector areas are smaller than 10 μm 2 within an oxide isolated structure. A relation between maximum injector current density and device size is derived.

DC characteristics of analogue compatible I3L transistors†

A technology of isoplanar integrated injection logic (I3L) is discussed. High packing density and high performance are achieved in this approach by use of various process innovations combined with topological design variations. The processing and DC characteristics of I3L structures integrated with common analogue circuit elements are studied. In this linear compatible I3L technology, inverted gain of 25 at 120 μ A collector current has been achieved with 8 x 8 μm2 collector area. Current gain of 45 and f T of more than 6 GHz are obtained with the analogue circuit transistor.

Design considerations of dense bipolar PLA's

Technology issues and circuit choices are addressed and the tradeoffs between density and performance are discussed. It is concluded that device density is of key importance to the overall circuit design of a programmable logic array (PLA). A very dense PLA can be designed with its decoder implemented using merged transistor logic circuits and array crosspoints using butted-emitter transistor layout.

The analysis and design of CMOS multidrain logic and stacked multidrain logic

A CMOS logic circuit called the CMOS multidrain logic (MDL) is proposed, analyzed, and experimentally observed. The basic circuit structure, which is derived from integrated injection logic, consists of an enhancement-mode MOSFET as a current injector and a multidrain MOSFET with drain terminals as output nodes and the gate terminal as input node. As compared with the multidrain NMOS logic, the difference is that an enhancement MOS instead of a depletion NMOS is used as a current injector.

Modelling and simulation of integrated circuits

Describing integrated circuits based on their physical and topological properties leads naturally to efficient algorithms and device models for circuit simulation. Physically based relaxation algorithms exploit the local and sparse nature of the circuit interconnect. Models that directly represent the processes of charge flow extend naturally to integrated circuit devices allowing the distributed nature of the integrated transistor to be represented. This approach has been used to develop models for metal oxide semiconductors (MOS) and bipolar transistors. The model for the bipolar transistor has been generalized to describe the multicollector merged device structures of integrated injection logic.

VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmetic

Computer simulations using SPICE establish the feasibility of implementing a highly pipelined high-speed FIR digital filter using Multiple-Valued Logic (MVL) Read-Only Memories (ROM's) to implement Residue Number System (RNS) Arithmetic in VLSI technology. A single VLSI chip can be used to convert from 8-bit binary to a 16-bit RNS with one additional chip to convert back. The basic approach proposed could be implemented in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I^{2}L</tex> , MOS, CMOS, or ECL technologies. A detailed design and simulation using ECL technology yields less than 20 000 gates and less than 13-W power dissipation per filter weight. A maximum throughput rate of 30 MHz can be achieved with an ECL design based on partitioning the circuit into 2.5 VLSI chips.per filter weight. A MOS or CMOS design can yield a considerable power savings with a corresponding reduction in throughput rate and number of VLSI chips while an (Integrated Injection Logic) <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(I^{2} L)</tex> design can achieve moderate speed and moderate power consumption with relative/low power supply voltages.