Analysis of Si:Ge heterojunction integrated injection logic (I/sup 2/L) structures using a stored charge model

Abstract

A quasi-two-dimensional stored charge model is developed as an aid to the optimization of SiGe integrated injection logic (I/sup 2/L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I/sup 2/L gate. Both the NpN switching transistor and the PNp load transistor are correctly modeled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I/sup 2/L and the Ge and doping concentrations varied to determine the important tradeoffs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NPN emitter layer. The inclusion of 16% Ge in the substrate-fed I/sup 2/L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable in SiGe I/sup 2/L even at a geometry of 3 /spl mu/m. The model is applied to a realistic, self-aligned structure and a delay of 34 ps is predicted. It is expected that this performance can be improved with a fully optimized, scaled structure.