Integrated Injection Logic Research Articles

Functional modeling of integrated injection logic—DC analysis

Dc analysis of integrated injection logic structures is performed. The analysis is bared on partitioning the basic I2L structure into injection and n-p-n transistor regions. One-dimensional approximation is assumed in obtaining the intrinsic and the extrinsic β u of the n-p-n transistor. The electric field in the epiregion has been considered and the analysis predicts the behavior of β u at an arbitrary current level. An effective efficiency λ for the injection region is also given. The results of the analysis are compared to practical measurements.

Selected bibliography on integrated injection logic (I2L)/merged transistor logic (MTL) technology

A selected bibliography is presented detailing the relevant technical literature describing the technology development and applications for integrated injection logic (I2L) and merged transistor logic (MTL).The period covered is, in effect, from 1971 to July 1977.

A Comparative Evaluation of Integrated Injection Logic

Radiation effects on integrated injection logic arrays are presented in terms of available data on "conventional" structures and new test data on advanced structures. The advanced structures were developed for improved electrical performance, independent of radiation hardness. These results are used as a basis of reviewing the considerations in hardened I2L development as an LSI technology in comparison to other contemporary LSI technologies.

The effect of current suppression in the pn−n+ diode of integrated injection logic

The j- V characteristics of the pn − n + diode are derived by combining the different current components in the n − region of the diode for various bias voltages. For infinitly fast recombination, the expression for the current density as a function of bias reduces to that of a conventional one-dimensional theory. For finite recombination, however, the expression deviates significantly from the usual expression. In fact, contrary to what would be expected from the conventional theory, the current increases as the width of the neutral n − region increases for a constant bias. Finally the results of the analysis of the pn − n + diode are applied to an analysis of the current gain in the integrated injection logic ( I 2 L) device. A qualitative discussion of the current gain for the lateral pnp transistor and for that of the vertical npn transistor is given.

Invited: I2L-Efficient Bipolar LSI Extension

By describing the evolution that lead to the invention of Merged Transistor Logic, MTL (=Integrated Injection Logic, I2L) in the IBM Laboratory, Boeblingen/Germany, it is underscored that I2L/MTL is not a new technology, but an extension of existing bipolar technology into LSI. A comparison of I2L/MTL with the n-MOS LSI contender shows considerable advantages of I2L mainly in power x delay (≈10 x), speed (≈2 … 4 x), and versatility (circuit mix, driving capability). From these features a very wide application spectrum results, reaching from consumer products to computers. Furthermore, a steady improvement of I2L has been observed. This includes circuit extensions, e.g. by Schottky diodes that lead MTL into the speed range of present TTL circuits.

Integrated injection logic (I 2L) : John Klinker. Proc. Internepcon. (Microelectron.) p. 114 (Oct. 19–21, 1976)

Integrated injection logic (I 2L) : John Klinker. Proc. Internepcon. (Microelectron.) p. 114 (Oct. 19–21, 1976)

Invited: Vertical Injection Logic –An Improved Structure of Integrated Injection Logic–

Vertical injection logic (VIL), an improved structure of integrated injection logic (I2L) with the vertical pnp injector, has shown the better electrical performances. The current gain α of the pnp transistor has been increased to 0.7∼1.0 in comparison with 0.4∼0.5 of usual one and this higher α in VIL has contributed to improve the power-delay product in the extrinsic region. The intrinsic delay time was also improved by the action of the bottom injector. The experimental results showed the minimum delay time of 6.5 ns and power-delay product of 0.07 pJ for VIL compared to 10.5 ns and 0.2 pJ for standard I2L. The capability of the very low power-delay product was examined with the wristwatch IC and the low propagation delay time was applied to the static RAM.

New v-groove integrated injection logic

A new V-groove integrated injection logic (v.i.i.l.) is proposed which combines the V-groove technology and the double-diffused bipolar technology. The fabrication processes arc qualitatively described. The lateral p–n–p transistor of the i.i.l. is located on the vertical V-shape surface, and the effective base width is controlled by the combination of the vertical diffusion process and the V-groove etching rate. A 1-dimensional analysis is used and an approximate expression for the collector current of the lateral p–n–p transistor is given. The v.i.i.l. is expected to have a higher production yield than that of the ordinary i.i.l.

The effect of current suppression in the [formula omitted] diode of integrated injection logic : S. Y. Yu and G. Thomas. Solid-St. Electron.20 (1), 19 (1977)

The effect of current suppression in the [formula omitted] diode of integrated injection logic : S. Y. Yu and G. Thomas. Solid-St. Electron.20 (1), 19 (1977)

Integrated injection logic: a bipolar LSI Technique

Integrated injection logic: a bipolar LSI Technique

An integrated injection logic (I/sup 2/L) macromodel including lateral and current redistribution effects

An integrated logic (I/SUP 2/L) macromodel for computer simulation of logical configurations of I/SUP 2/L gates is presented. The macromodel is synthesized from the familiar Ebers-Moll equivalent circuit which permits compatibility with numerous presently available circuit simulators. Measurement procedures are described for the complete and self-consistent set of electrical parameters required for macromodel definition. A five-stage ring oscillator is computer simulated to demonstrate the application of the macromodel. Lateral current transfer (LCT) between adjacent gates and injector current redistribution (ICR) effects are shown to reduce gate propagation delay times. When both effects are included, the macromodel produces an agreement between computer simulated and experimental results of better than 10 percent. A ring oscillator example illustrates the use of the macromodel to provide physical insight into the layout sensitivity of I/SUP 2/L.

High-performance integrated injection logic: a microprogram sequencer built with I/SUP 3/L

A microprogram sequencer is described. Its role in a systems environment is indicated. Functional details of the device including its instruction set are given. A newly developed technology isoplanar integrated injection logic (I/SUP 3/L) is discussed. Emphasis is placed on methods to achieve the required high performance. Details of the device structure and layout techniques are included. The resulting speed performance is indicated and general parameters are displayed.

Vertical injection logic

Vertical injection logic (VIL) is a novel form of integrated injection logic (I/SUP 2/L). A vertical p-n-p transistor is used in place of a lateral p-n-p transistor to obtain an improved performance at the same packing density as conventional I/SUP 2/L. The current gain of the p-n-p transistor can be increased, which leads to the excellent power-delay product. The intrinsic delay time is also improved by the action of the bottom injector as a hole sink. The fabrication process and electrical characteristics of VIL are described and contrasted with conventional I/SUP 2/L. A tentative hole sink model is also proposed. The experimental results showed the minimum delay time of 8.8 ns and the power-delay product of 0.07 pJ at low power level below 1 /spl mu/W for VIL compared to 25 ns and 0.18 pJ for standard I/SUP 2/L.

Folded-collector integrated injection logic

Folded-collector I/SUP 2/L offers an effective method of controlling the saturation of the n-p-n transistor simply by controlling the ratio of two areas: the area of the output collector(s) and the area of a `dummy' collector. This extra collector is folded back and connected to the input base. The structure improves the minimum delay of the basic I/SUP 2/L gate. Moreover, the structure has many circuit applications where a current scaling factor is required, e.g., threshold and ternary logic. Some of these circuits are given.

Current state of microprocessors

An overview of the current state of microprocessor development is given. The impact on design engineers and the semi-conductor industry has been revolutionary, yet microprocessors are earnestly accepted. Several reasons for this acceptance are offered. Basic microprocessor architecture is reviewed. The current state of the semiconductor technology indicates that integrated injection logic (I 2 L) is the most promising. Software development is still in its infancy and is a major obstacle to gaining a general class of users (other than presently predominant design engineers). With further development in hardware and software technologies, microprocessors will find an enormous range of applications.

High speed integrated injection logic (I/sup 2/L)

High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.

Solid state: I-squared L: A happy merger: Integrated injection logic is a fine example, if not the first, of how to gain high efficiency in semiconductor device design

Integrated injection logic is a fine example, if not the first, of how to gain high efficiency in semiconductor device design.

Cost, Performance, and Size Tradeoffs for Different Levels in a Memory Hierarchy*

Until recently, electronically addressable devices such as ferrite core, plated wire, semiconductor memories, and electromechanically addressable devices such as magnetic tapes, disks, and drums were the few technologies from which a computer system designer could build a memory system. A number of different new technologies and devices have been developed that close the "access gap" <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> between the two dissimilar technologies mentioned above. These include charge-coupled devices (CCD's), <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> bubble memories, <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> electron beam addressed memories (EBAM), <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> and domain tip propagation (DOT). <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">16</sup> Other technologies like CMOS <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> and integrated injection logic (I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L), <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> compete directly with the existing technologies. Table 1 (see p. 46) shows the possibility of a six-level hierarchy and some cost and performance projections for these technologies.

Integrated Injection Logic: A Bipolar LSI Technique

Integrated injection logic or merged transistor logic is a novel bipolar circuit design approach to achieve high-density large-scale integration. As the basic logic units it uses multicollector npn transistors which are powered from merged multicollector lateral pnp transistors. I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L can be fabricated with standard buried collector technology and is therefore compatible with conventional bipolar circuitry on the same chip. The feature of having special interface circuitry—digital and/or linear—on the same chip renders I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L a powerful LSI technique.

Radiation Effects Modeling and Experimental Data on I2L Devices

This paper reports on an Integrated Injection Logic (I2L) radiation effects model which includes radiation effects phenomena. Twenty-five individual current components were identified for an 12L logic gate by assuming wholly vertical or wholly horizontal current flow. Equations were developed for each component in terms of basic parameters such as doping profiles, distances, and diffusion lengths, and set up on a computer for specific logic cell configurations. For neutron damage, the model shows excellent agreement with experimental data. Reactor test results on GE I2L samples showed a neutron hardness level in the range of 6 x 1012 to 3 x 1013 n/cm2 (1 MeV Eq), and Cobalt-60 tests showed a total dose hardness of 6 x 104 to greater than 1 x 106 Rads(Si) (all device types at an injection current of 50 microamps per gate). It was found that significant hardness improvements could be achieved by: a) diffusion profile variation, b) utilizing a tight N+ collar around the cell, and c) locating the collector close to the injector. Flash X-ray tests showed a transient logic upset threshold of 1 x 109 Rads(Si)/sec for a 28 ns pulse, and a survival level greater than 2 x 1012 Rads(Si)/sec.