Fan-out Wafer Level Packaging Research Articles

M-Series with Adaptive Patterning for High-Yield Fan-Out SIP

Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.

2.5D / 3D IC Landscape: Market and Technology Trends

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain and continue to be investigated, the spotlight is turning to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D / 3D IC solutions together with upgraded flip chip BGAs aim to revive the cost/performance curve and extend both scaling and functionality roadmaps. Future packages need to tackle the explosion in information exchange translating to high number of I/Os and be able to support heterogeneous integration. This puts particular pressure on die to board interconnects. Technologies to fill the void created in diverging PCB versus IC feature sizes are constantly under development. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect, considered today the most advanced technology, is one emerging option that aims to enable heterogeneous integration. Such a technology is not limited to CMOS scaling in itself, it is rather based on bringing more functionality by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components…) while reducing the package form factor. This functional diversification is also known as More-than-Moore. This work focuses on the analysis of recent developments and future trends of the 2.5D / 3D IC landscape. What's new since last year? TSV technology has already been utilized for several years within the MEMS and CMOS image sensor (CIS) market, but the news is that it finally seems to be happening within the logic and memory domain. Latest products such as AMD Radeon R9 Fury with its 2.5D configuration including HBM stacks and Samsung 3D TSV stacked DRAM, among others, aim for high volume. Fueled by consumer applications such as smartphones and tablets, the MEMS and CIS markets are expected to exhibit continuous growth over the next several years, while in the high-end market, driven by the need for further performance increase, volatile memory and especially DRAM are finally opening the doors of 2.5D / 3D IC commercial adoption. This analysis will cover 2.5D interposer & 3DIC platforms as well as MEMS and CIS TSV packaging. Market forecasts in terms of wafer starts, market revenue, application segments and end-products will be presented. Furthermore, supply chain activities and major player interactions will be analyzed and 3D integration technology roadmaps will be reviewed. In conclusion, this study will aim at providing comprehensive insight into 2.5D / 3D IC market and technology trends.

Packaging and Assembly Challenges for 2.5D/3D Devices

The continuous development of 2.5D/3D packaging and stack assembly technologies has enabled different ways of producing advanced packages for the said devices. Advancement in D2D, D2W and W2W bonding have allowed these devices to be a step closer to being fully manufactured in volume. Thermo-compression bonding (TCB) process in combination with a pre-applied underfill material (WLUF/NUF) have been developed and investigated for assembling 2.5D and 3D devices with fine pitch (10μm - 40 μm) μbumps. This assembly step though developed, is not without challenges. There is a need to select the right underfill material based on its mechanical and chemical properties which could contribute to issues such as die warping, voiding and non-wetting of μbumps. These materials should also be able to withstand several thermal steps within the entire stack assembly process and is able to pass reliability testing. During the TCB process, bonding forces have a profound impact on the joint formation behavior on the μbumps. A low bonding force could produce a joint formation with a lot of underfill filler entrapment and an incomplete reaction of the solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted intermetallic compound (IMC) layer in the joints. The D2D, D2W and W2W assembled chips can then be packaged into a standard flip chip component using laminate BGA substrates. But even with this volume manufacturing process, the introduction of 2.5D/3D stack devices brings another set of challenges to an existing assembly infrastructure. Challenges such as the handling of the stacked devices, the CTE mismatches of an entirely new set of materials and the constant scaling in FC bump (Cu Pillar or C4) pitches in an existing infrastructure remain. The limitations of organic BGA packages in terms of CTE mismatches and costs gave rise to Fan-out Wafer Level Packages (FOWLP) or a technique also known as wafer reconstruction. However, there are certain tradeoffs particularly in the molding process step of fully D2W stacked or reconstructed 300 mm wafers. Molding such a large area of stacked chips with very narrow gaps of around 50μm to 300μm is a major challenge especially in trying to maintain the flatness of the wafer for succeeding wafer level processing steps. The large warpage of over molded (D2W or reconstructed) wafers is due to the coefficient of thermal expansion (CTE) mismatch between silicon and the reconstruction material. Therefore careful selection of materials and design of reconstructed structures is needed. Other techniques to keep the D2W or reconstructed assemblies are being developed and evaluated. Also by selecting an FOWLP or reconstructed wafer type of package, the integration of temporary bonding materials (TBMs) in TCB and wafer molding becomes a challenge. In order to produce the reconstructed wafer or the thinned D2W assembly, thermal and mechanical stability is required for such a material. In summary, the combination of advance stacking techniques and materials within certain 2.5D/3D integration flows could produce a low-cost and reliable 3D package. But these combinations will pose a number of challenges that needs to be addressed. This paper will discuss the different integration flows, stacking and packaging assembly techniques (and their challenges) that could make volume manufacturing possible for 2.5D/3D devices in the future.

Evaluation of High-Speed Copper Plating Products for RDL, Micropillar, and Fan-Out Applications

Increasing market demand for portable high-performance electronic devices is requiring an increase in the I/O density in the chip packaging used to make these products. Flip-chip interconnects that enable advanced packaging utilize a C4 bumping process with lead-free solder to make the chip interconnection. However, with the decreasing chip size and tighter I/O pitch requirements that are needed to realize high-performance, Cu pillar plating has emerged as an enabling technology to meet the technical demands. Cu pillars, capped with a lead-free solder, allow for increased I/O density while still maintaining the standoff needed for proper thermal and electrical performance of stacked chips. With this realized performance, there is expected to be a significant increase in capacity of Cu pillar in the industry, requiring electrolytic Cu plating products with fast deposition rates in order to decrease wafer plating time and increase throughput. In this paper, Cu electroplating products are evaluated for plating performance at increased deposition rates for Cu pillar applications ranging from micropillar (<20 μm feature size), to standard pillar (20 – 75 μm feature size), redistribution layer (RDL) wiring, and the emerging fan-out wafer level packaging (FO-WLP), which encompasses megapillars (>150 μm feature sizes) as well as stacked via RDL designs. The chief performance criteria for evaluation is the ability to increase deposition rates while maintaining feature height uniformity, smooth and uniform feature morphology, and ability to plate a wide variety of feature sizes and shapes. Additionally, performance of these products is assessed on their ability to plate highly pure Cu deposits which enable void-free integration with lead-free solder without the need of (but is compatible with) a cost-added barrier layer.

Fan-in WLP: Technology and Market Trends

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

Advanced Manufacturing Technology for Fan-Out Wafer Level Packaging

Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid error due to die placement errors.

Verification of Faulty Mechanism for Fan-Out Wafer Level Package Using Numerical Analysis

The manufactures of the ultra-thin and smaller semiconductor chip are required over the portable electric devices. The investigation of Fan-out wafer level package (FOWLP) is used widely, among the performance improvement and miniaturization technologies. In this paper, we obtained lots of crack near the passivation (PSV) and redistributed layer (RDL) region of FOWLP during the reliability evaluation of thermal cycling test (TCT). The generated stress and deformational behavior was observed through 2D finite-element analysis. The concentrated stress and deformational behavior are observed around the Solder ball edge and RDL & PSV edges. The crack was observed experimentally as well. The verification of the mechanism for crack generation and the validity of the finite-element analysis were verified by the structural analysis.

Development of Mold Compounds With Ultralow Coefficient of Thermal Expansion and High Glass Transition Temperature for Fan-Out Wafer-Level Packaging

Coefficient of thermal expansion (CTE) mismatch between an underfill encapsulant material and integrated circuit chips mounted on a substrate is the major reason for device failure in a fan-out wafer-level packaging (FOWLP) assembly. In this paper, a variety of moldable polymer composite systems with evenly dispersed dielectric nanoparticles or microparticles and minimal cure shrinkage for FOWLP assemblies have been investigated. Most importantly, a low CTE of 6.6 ppm/°C and a high glass transition temperature ( $T_{g}$ ) above 300 °C were achieved through a processing methodology that exhibits fairly good repeatability. A special surfactant treatment of the particle surfaces has played a crucial role in further enhancing the thermomechanical properties, yield, and repeatability of the composite material.

Design and Optimization of Wafer-Level Compression Molding Process for One Chip Plus Multiple Decaps

Decaps are the panacea for the noise-related issues. Due to the short distance advantage, decaps are embedded in the fan-out wafer-level package instead of the printed circuit board. These decaps, generally thicker than chips, will have a crucial influence on the molding process as well. A lot of issues are encountered in the molding process, especially with lots of decaps, i.e., voids issues, incomplete filling issues, and die shift issues. In an optimized design, all these issues should be prevented or reduced as much as possible. In this paper, design flow for the wafer-level molding process is demonstrated and design guidelines are provided. Three important evaluation standards are used to evaluate the design, i.e., incomplete filling, drag force, and voids. Two kinds of design parameters, structure parameters (i.e., die placement, die size and thickness, and so on) and process parameters (i.e., vacuum pressure, filling speed, and so on), are optimized in the whole study. Optimization of these parameters helps the real wafer-level molding process to be conducted smoothly.

COMPARISON OF FOWLP VS QFN PACKAGE FROM THERMAL ASPECT

The QFN package dominates IC industry with a small number of IOs due to its simplicity, maturity and low cost in mass production. However, as the industry progresses toward portability and smaller size, thinner and more compact packages such as Fan Out Wafer Level Package (FOWLP) is a better option/solution than QFN package. Due to its flip chip configuration, imbedded redistribution (RDL) interconnection and elimination of die attach layer, the FOWLP package has potential to surpass QFN package in thermal performance. This paper utilized a typical 3-stage RF power amplifier die as a thermal test vehicle, packaged with FOWLP and QFN, built FEA (Finite Element Analysis) thermal models and analyzed the thermal performance by thermal resistance breakdown and thermal bottleneck identification. Comparison of FOWLP and QFN shows that the heat paths and bottlenecks within each package are quite different. In QFN package, bottleneck lies in the die attach layer while in FOWLP package, it lies in the backend layers on the die and the RDL vias. FOWLP package may also require better thermal vias performance in PCB due to smaller footprint of LGA/Solder. Large horizontal heat spreading in a poorly design PCB may offset the thermal advantages in FOWLP package. The simulation results of both packages have good correlation with Infrared (IR) measurement of corresponding thermal test vehicles.

Silicon Wafer Integrated Fan-out Technology

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed. A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT package technology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single & multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer level packaging technique. This can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enables the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

Advancements in Phenomenological Understanding of Thinning and Planarization Processes for TSV-Enabled 2.5-3D Device Fabrications

Innovations and novel development in substrate thinning and planarization processes driven by advanced packages fabrications are surveyed. For direct 3D die-stacking process approach, a novel methodology for bonded wafer grinding has been put in place based on feedforward wafer thickness metrology and in-situ Auto-TTV Adjustment grinding. This scheme can minimize post-thinning RST variations leading to downstream TSV process improvements. For over-mold facilitated, multi-functional packages and wafer-level fan-out packages, grinding process improved in ways of fixed abrasives and equipment automation. For glass devices processing, new grinding and polishing have been developed on existing Si-compatible equipment. For ductile materials planarization, the surface planer process is presented.

Adhesive Enhancement Technology for Directly Metal Plating on EMC

Plating on molding compound is a relatively new field with many possible applications. One major application is magnetic or electrical EMI shielding of active components. This is currently done by metallic cans. However, this technique also increases the space requirements. A second major application, is the formation of build-up circuits on encased components, such as for Fan-out Wafer Level Packaging (FO WLP). An established method to provide a metallic seed layer is sputtering. However, with respect to cost effectiveness and mass production capability, classical electroless metallization along with an adhesion promoters would a desirable alternative. In this paper we will present a new approach, where components encased by molding compound are directly coated with an electroless copper or nickel layer. By this method spatial requirements are minimized. Also, this process fits into the existing infrastructure within the PCB industry. Due to the presence of fillers with an extremely high ratio (70–90%wt.) and irregular size (from few μm to tens of μm), classical Desmear followed by electroless seeding can get at best an adhesion of only 2–3N/cm . This is typically insuffient to prevent delamination during further processing. In contrast, with chemically bonding adhesion promoters, as presented in this paper, we are able to get up to 5N/cm of peel strength without any blistering. The plated layer stands up well to reflow shock (260C) and HAST without significant loss of adhesion. These adhesion enhancement technology is applicable to various kinds of molding compound. Extending this technology to FO WLP (i.e. FO SiP, FO PoP) can be another far reaching application.

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).

(Invited) Development of Advanced Fan-Out Wafer Level Package

Fan-out WLP is one of embedded package processed on wafer level, also a key advanced packages with higher number of I/Os, integration flexibilities. Furthermore, it enables to integrate multiple dies vertically and horizontally in one package without using substrates. Thus, recently Fan-out WLP technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. Not only the electronic packages, Fan-out WLP but also is used for sensor, power IC and LED packages This paper reports developments of next generation Fan-out WLP for advanced packaging solutions.

Warpage Prediction and Experiments of Fan-Out Waferlevel Package During Encapsulation Process

A wafer level package (WLP) that has a flip chip form and uses thin-film redistribution with solder bumps to connect the package to the printed wiring board directly is discussed in this paper. A liquid molding compound is used for the encapsulation process. Since the thickness of the fan-out WLP is smaller than that in a traditional integrated circuit (IC) package, the fan-out WLP induces more serious warpage. Warpage plays an important role during the IC encapsulation process, and too large a warpage would not let the package proceed to the next manufacturing process. This paper uses an approach that considers both cure- and thermal-induced shrinkages during the encapsulation process to predict the amount of warpage. Cure-induced shrinkage is described by the pressure-volume-temperature-cure (PVTC) equation of the liquid compound. The thermally induced shrinkage is described by the coefficients of thermal expansion of the component materials. The liquid compound properties are obtained by various techniques, such as cure kinetics by differential scanning calorimetry- and cure-induced shrinkage by a PVTC testing machine. These experimental data are used to formulate the PVTC equation. A fan-out WLP is first simulated, and the simulation results are verified with experiments. It is shown that an approach that considers both thermal and cure/compressibility effects can better predict the amount of warpage for the fan-out WLP. The PVTC equation is successfully implemented, and it is verified that warpage is governed by both thermal and cure shrinkages. The amount of warpage after molding could be accurately predicted with this methodology. Simulation results show that cure shrinkage of the liquid compound is the dominant factor responsible for package warpage after encapsulation.

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

Advanced warpage characterization for FOWLP

Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer height range or the mean surface wafer center height, respectively [1]. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties [2]. In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability [3]. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps [3]. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.

Robust Reliability Performance of Large size eWLB (Fan-out WLP)

With reducing form-factor and functional integration of mobile devices, Wafer Level Packaging (WLP) is attractive packaging technology with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP, it is more optimal and promising solution compared to fan-in WLP, because it can offer greater flexibility in design of more IOs, multi-chips, heterogeneous integration and 3D SiP. eWLB (embedded wafer level packaging) is a type of fan-out WLP enabling applications that require smaller form-factor, excellent heat dissipations, thin package profile as it has the potential to evolve in various configurations with proven manufacturing capacity and production yield. This paper discusses the recent advancements of robust reliability performance of large size eWLB. It will also highlight the recent achievement of enhanced component level reliability with advanced dielectric materials. After a parametric study and mechanical simulations, new advanced materials were selected and applied to eWLB. Standard JEDEC tests were carried out to investigate component level reliability of large size (9x9~14x14mm2) test vehicles and both destructive/non-destructive analysis were performed to investigate potential structural defects. Daisychain test vehicles were also tested for drop and TCoB (Temperature Cycle on Board) reliability performance in industry standard test conditions. Besides, this paper will also present a study of package level warpage behaviour with Thermo-Moire measurement.

Reliability and Performance Improvements of 3D System-in-Packages in Fan-Out Wafer Level Packaging

Recent development efforts for fan-out wafer level packaging (FO-WLP) have focused on system-in-package (SiP) solutions using both 2D and 3D packaging structures. Creating connections between the various elements of the system is one of the critical requirements of the packaging technology. The connections must provide a low loss pathway, exhibit manufacturability and prove reliable. Effective system connections enable complex yet volumetrically and electrically efficient systems to be constructed. The combination of various system elements including, but not limited to, SMDs, CMOS, GaAs, MEMS, power devices, imaging sensors or IPDs gives system designers the capability to generate novel systems and differentiating solutions. Both 2D and 3D SiPs based upon the Redistributed Chi Package (RCP) have been developed for consumer, defense and medical applications. In RCP (i.e. FO-WLP), 2D systems are readily achieved through the use of existing packaging processes, materials and structures. For 3D embodiments, the FO-WLP technology must be expanded. 3D integration in FO-WLP can be achieved with the use of package-on-package (PoP), embedded substrates, package edge connections, die stacking or even TSV approaches. However, a more typical solution to the 3D integration challenge is the through package via (TPV). TPVs can resemble substrate vias but their construction is typically different. Regardless of materials selected or processes used to create the TPV, system connections using a TPV will require a certain level of performance and reliability. Reliability and performance improvements to the 3D RCP technology will be presented.