Packaging and Assembly Challenges for 2.5D/3D Devices

Abstract

The continuous development of 2.5D/3D packaging and stack assembly technologies has enabled different ways of producing advanced packages for the said devices. Advancement in D2D, D2W and W2W bonding have allowed these devices to be a step closer to being fully manufactured in volume. Thermo-compression bonding (TCB) process in combination with a pre-applied underfill material (WLUF/NUF) have been developed and investigated for assembling 2.5D and 3D devices with fine pitch (10μm - 40 μm) μbumps. This assembly step though developed, is not without challenges. There is a need to select the right underfill material based on its mechanical and chemical properties which could contribute to issues such as die warping, voiding and non-wetting of μbumps. These materials should also be able to withstand several thermal steps within the entire stack assembly process and is able to pass reliability testing. During the TCB process, bonding forces have a profound impact on the joint formation behavior on the μbumps. A low bonding force could produce a joint formation with a lot of underfill filler entrapment and an incomplete reaction of the solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted intermetallic compound (IMC) layer in the joints. The D2D, D2W and W2W assembled chips can then be packaged into a standard flip chip component using laminate BGA substrates. But even with this volume manufacturing process, the introduction of 2.5D/3D stack devices brings another set of challenges to an existing assembly infrastructure. Challenges such as the handling of the stacked devices, the CTE mismatches of an entirely new set of materials and the constant scaling in FC bump (Cu Pillar or C4) pitches in an existing infrastructure remain. The limitations of organic BGA packages in terms of CTE mismatches and costs gave rise to Fan-out Wafer Level Packages (FOWLP) or a technique also known as wafer reconstruction. However, there are certain tradeoffs particularly in the molding process step of fully D2W stacked or reconstructed 300 mm wafers. Molding such a large area of stacked chips with very narrow gaps of around 50μm to 300μm is a major challenge especially in trying to maintain the flatness of the wafer for succeeding wafer level processing steps. The large warpage of over molded (D2W or reconstructed) wafers is due to the coefficient of thermal expansion (CTE) mismatch between silicon and the reconstruction material. Therefore careful selection of materials and design of reconstructed structures is needed. Other techniques to keep the D2W or reconstructed assemblies are being developed and evaluated. Also by selecting an FOWLP or reconstructed wafer type of package, the integration of temporary bonding materials (TBMs) in TCB and wafer molding becomes a challenge. In order to produce the reconstructed wafer or the thinned D2W assembly, thermal and mechanical stability is required for such a material. In summary, the combination of advance stacking techniques and materials within certain 2.5D/3D integration flows could produce a low-cost and reliable 3D package. But these combinations will pose a number of challenges that needs to be addressed. This paper will discuss the different integration flows, stacking and packaging assembly techniques (and their challenges) that could make volume manufacturing possible for 2.5D/3D devices in the future.