Abstract
Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid error due to die placement errors.
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