Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration.

Steve Voges,Ole Hoelck,Karl-Friedrich Becker,Ruben Kahle,Martin Schneider-Ramelow,Tanja Braun,Marc Dreissigacker

doi:10.3390/mi10050342

Abstract

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

Highlights

Within the European funded project smart-MEMPHIS, the goal was to tackle the main challenge for all smart devices—becoming self-powering
The project was aimed to design, manufacture and test a miniaturized autonomous energy supply based on harvesting vibrational energy with piezo-MEMS energy harvesters
Cost effective packaging was needed for the 3D system integration of a MEMS-based multi-axis energy harvester, an ultra-low-power application-specific integrated circuit (ASIC) to manage the variations of the frequency and harvested power, and a miniaturized energy storing supercapacitor [1,2]

Summary

Introduction

Within the European funded project smart-MEMPHIS, the goal was to tackle the main challenge for all smart devices—becoming self-powering. Cost effective packaging was needed for the 3D system integration of a MEMS-based multi-axis energy harvester, an ultra-low-power ASIC (application-specific integrated circuit) to manage the variations of the frequency and harvested power, and a miniaturized energy storing supercapacitor [1,2]. Miniaturization was another key demand as target applications were a leadless pacemaker and a wireless sensor network for structural health monitoring. Manicsrwomearchsinaens d201t9e,c1h0n, xoFloOgRiePsE.ERTRhEeVmIEaWin goal is miniaturization, but the increased component de2nosfi1ty0 and performance, simplification of design and assembly, flexibility, functionality and, cost and tTimhee-dtroi-vmerasrkfoert, 3hDavpeabckeaenginfogusnodluttoiobnestahree cmoraendifroilvde,rasnfdoregacohinrgeq3uDiraesmweneltl.caBllessifdoersddififeeraenndt apnascwkaegres satnadcktiencghannodlofgoiledse.dTpheacmkaagines,geomalbiesdmdiinngiadtuiersiziastaiokne,ybtuetchthneoliongcyrefaosrehdecteormogpeonneeonutsdseynstseitmy ainntdegpreartifoonrm[3a]n. A lot of activities that are runnTinhgerwe oarrledtwwiodemdaeinalawppitrhoafachne-osufot rweamfebreldedveedl idniteegtercahtinoonl.ogMieasi:nfaanp-poruotawchaefesrhleerveelinpcalcukdaegitnhge (eFmObWedLdPe)d, wwhaefreer ldeiveesl abraellegmribdeadrdready (ienWtoLpBo)lbyymIenrfiennecoanps[6u]l,atnhtes,InanFdO PpCacBka(pgreinbtyedTScMircCu[it7]booratrhde) eremdbisetdridbiuntge,dwchheiprepdacieksagaere(ReCmPb)ebdydeFdreeinstcoalpe r[i8n]t.eFdanci-rocuutitwbaofearrdlesv[e4l,5p]a.cAkalgoitngof(FaOctWiviLtiPe)shtahsatbeaerne rinuintinaitnegd iwnovroldluwmideeprdoedaul cwtiiotnh ffoarnm-ooubtilwe aafnedr wlevireelleisnsteagprpaltiicoanti.oMnsa(imn aaipnplyrowaicrheelessshebraeseibnacnluddse) atnhde eismnboewddmedovwinagfeirntloevaeultboamllogtirvide aanrrdaym(eedWicLaBl a) pbpyliIcnaftiinoenosn. [6], the InFO package by TSMC [7] or the redisOtrinbeudterdivcehripfopr apcaknaeglele(RveClPp)abcykaFgreinegsciasleno[8w]., Foafnc-oouurtswe,atfheer lloevweelrpinagckoafgcinogst(sFbOyWinLcPre)ahsains gbetehne ipnaictikaategdinign sviozleufmroemprwodafuecrtsioton lfaorrgmeropbailneealnfdorwmiraetsleasns daptphleirceabtiyoninsc(rmeaasiinnlgy wthierenluesms bbearseobfapnadcsk)aagneds ims annouwfamctouvriendgiinntpoaaraultloeml. oAtidvdeiatinodnamlleyd, PicLaPl ahpapslitchaetioopnps.ortunity to adapt processes, materials and equipOmneendtrfirvoemr footrhpear nteeclhlenvoelol gpyacakraegasin. gPrisinnteodwc,iorcfuciotubrosaer,dth(ePCloBw),elriiqnugidofcrcyossttaslbdyisipnlcaryea(LsiCngD)thoer psoalcakraegqinugipsmizeenftroamre wmaafneursfatcotularregderonpapnaenleflosrimzeastsaannddatlhsoeroeffbyerinncerweaaspinpgrothacehneusmfobrefraonf-opuatckpaagneesl mlevanelupfaacctkuargeidngin(FpOarPaLllPe)l.[9A–d1d1]i.tionally, PLP has the opportunity to adapt processes, materials and equipFmigeunrtef1rosmhoowthsearnteocvhenrovlioegwyoafrethase.tPyrpinictaeldpcainrceul istizbeosarudse(PdCinB)P, CliqBuainddcrLyCstDalmdiasnpulafayc(tLuCriDng) oinr scoolmarpeaqriusiopnmteonsttanredamrdanwufaafcetrusriezdeso. nThpiasnaelresiazdeys iannddicaaltseosothffeervnareiwetyapopf rpooascshibeslefoforrfmana-tosuwt ipthaonuelt lteavkeinl gpathckeatgeicnhgni(cFaOl PchLaPl)le[n9g–1e1s]a.nd possible limitations for FOPLP into account

Process Considerations

Materials and Methods

RReessuullttss aandd Discussion