Fan-out Wafer Level Packaging Research Articles

Warpage Prediction and Optimization for Embedded Silicon Fan-Out Wafer-Level Packaging Based on an Extended Theoretical Model

The fan-out package is designed to provide increased I/O density within a reduced form factor at a lower cost, as well as good electrical performance and heterogeneous integration capabilities, which has gained significant attention in recent years. However, warpage control during manufacturing process is a key character for fan-out packages. This paper focuses on the warpage prediction and optimization of embedded silicon fan-out (eSiFO) wafer-level package. An extended theoretical calculation model is applied and demonstrated, and the effects of various parameters on warpage were analyzed for optimization. By comparison with the experimental results, the finite-element modeling (FEM) simulation results and classic bimaterial model, the proposed extended theoretical calculation model is proven to be simple, fast, and effective for eSiFO wafer-level package. The effects of process steps, structural parameters, and material parameters were studied based on the extended theoretical model, and some advice on reducing warpage was given in the end. This paper offers an insight work for the warpage study of other embedded and fan-out packages.

Process and characterization of photo-definable organic–inorganic dielectric for wafer level packaging

The introduction of an organic–inorganic dielectric material into the redistribution layers in fan-out wafer level packaging technology has been investigated to improve mechanical stress, thermal stability, and electrical breakdown compared to organic dielectric materials. A photo-definable organic–inorganic dielectric material called polysilsesquioxane (PSSQ) has been studied in this work. The photo-definable PSSQ dielectric allows a simultaneous UV patterning and curing process. A PSSQ sample was prepared by spin-coating on a 6-in. Si wafer, pre-baking at 100 °C for 5 min, UV exposure, and then PGMA developing. The cured PSSQ films have a dielectric constant from 2.0 to 2.38 and dielectric loss from 0.0001 to 0.005. In addition, the 2 μm line patterns were obtained after 10 min of UV exposure. It has been demonstrated that PSSQ dielectric materials can provide excellent process capability of simultaneous UV patterning and curing process.

Evaluation of fan-out wafer level package strength

PurposeThe fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack.Design/methodology/approachThis paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point.FindingsThe results show that the backside protection tape does not have the ability to enhance the FOWLP strength, and the strength of over-molded structure FOWLP is superior to that of other structure FOWLPs with the same thickness level.Originality/valueThere is ample research about the silicon strength and silicon die strength. However, there is little research about the package level strength and no research about the FOWLP strength. The FOWLP is made up of various materials. The effect of individual component and external environment on the FOWLP strength is uncertain. Therefore, the study of strength behavior of FOWLP is significant.

Quick Prototyping Design for More than Moore era

[Background and Motivation] System in Package (SiP) is pulling the evolution of technology instead of deep submicron of LSI. SiP assists coming AI/IoT/5G world. SiP has many implementation variations. When we examine the chip and package implementation technique for the target product, it's important task to find the optimal solution for the product considering trade-off between cost and performance. Compared with mass production products, it's important to optimize costs especially for small volume production products. Moreover, in terms of performance, compared to conventional packages, for high frequency products and SiP, since the margin becomes small and confirming system level electrical characteristics are necessary, in addition to conventional conceptual design and detail design, prototyping design is required to test its electrical characteristics while keeping lower cost. [Technical callenge] To do prototyping design at the early stage of product and find the optimum solution of the product, we created short turn-around time(TAT) iteration environment and distributed prototyping design. Quick Prototyping, which is a short TAT iteration environment, is based on the LSI/Package/PCB integrated co-design environment, estimates the chip size from the signal number of product, performs LSI design prototyping, using package automatic net assignment and the substrate auto routing, proceeds package prototype design and then confirms electrical characteristics. In the above, itfs possible to consider multiple implementation variations. In the distribution of prototype design, we utilize the LPB format (IEC 63055/IEEE 2401), have eliminated the interface(I/F) barriers between companies and tools, and have developed an environment for design prototypes and checking their characteristics throughout the industry. [Results and Conclusions] In collaboration with Semiconductor vendor Socionext Inc., as the above benchmark, 3D Flip Chip-Chip Scale Package(FCCSP) (with memory package with Package on Package(PoP) method) and 3D Fan-Out Wafer Level Package(FOWLP) (similarly in PoP method) as samples, the prototype design was created out. By comparison of the electrical characteristics, the Self Inductance of the FOWLP becomes half or less than FCCSP, the power supply noise could be suppressed. The shielding effect of FOWLP reduced the influence of crosstalk. We confirmed that FOWLP has advantage of electrical characteristics. On the cost side, in the LSI implementation of the FOWLP side, only the function blocks requiring performance were replaced with the fine node by chip partitioning, we examined to suppress the increase in cost while maintaining the performance advantage of FOWLP. With Quick Prototyping, cost and performance balance can be examined in the product review early stages, also by utilizing the LPB format for Quick Prototyping, from the negotiation stage with business partners, we can share the design data, focus on tuning the product itself and improve the competitive SiP products.

The bifurcation of advanced packaging

Following a similar trend from the 1990's, IC package design is experiencing a sea change. As a refresher, the 1990's is when the ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of the BGA. In short, the BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. On top of that, IO's were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs. As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved! Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace, are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking and, in some cases, chips being packaged directly at the wafer-level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like, 2.5D/3D IC and fan-out wafer-level packaging (FOWLP). Instead, in all likelihood IC design tools and flows will need to be slightly adapted to support the next generation of package designs. Let's start with foundry-based FOWLP. In this case, induvial dice are placed on a chip-carrier with additional spacing between them. Molding is poured in the empty space and then an array of bumps (UBM) and the connectivity (RDL) are added. In foundry-based flows, these UBM and RDL layers require IC-styled routing/metal fill and mask generation from the layout tool. In addition, these masks must be verified with traditional IC DRC/LVS tools. It's clear that some kind of hybrid advanced packaging flow using some traditional IC tools in the flow is required to support this type of design. And in fact, if you look at the largest semiconductor foundries reference flow tools, you will find this to be true. This presentation further examines the design tool/flow requirement for FOWLP, 2.5D/3D IC and future multi-die packaging technologies.

Ultra-low Warpage and Anhydride-free Liquid Compression Molding Materials for Advanced Semiconductor Packaging

Advanced semiconductor packaging landscape is rapidly evolving to accommodate requirements of front end node shrink and performance expectations from emerging applications in big data, artificial intelligence, mobile and autonomous driving. Multiple innovations in packaging process technology as well as processing materials enable the progress in advanced packaging. Several wafer level packaging (WLP) platforms have emerged recently using fan-in, fan-out, 2.5D and 3D packaging processes to satisfy the requirements of increased functionality, reduced form factor, lower power consumption, and high reliability. These often-conflicting requirements drive the design and development of many new electronic materials including liquid compression molding (LCM) for Fan-In and Fan-Out WLPs. Historically, anhydride-based LCM materials have been used to balance the material properties to achieve consistent dispensability, high quality molding, and high mechanical stability during grinding, RDL, and singulation processing. However, stricter environmental regulations driven by EU REACH stipulates complete replacement of anhydride resins with more environmentally friendly raw materials while still providing the same or better performance. Most recently, Henkel has developed new platforms of anhydride-free LCM materials with reduced cure shrinkage, ultra-low warpage, good chemical resistance, and high reliability. LCM material choice is integral to the package design and end use as this material needs to withstand several thermal, mechanical, chemical and vacuum processes during the construction of the package and stringent reliability conditions. By judicious construction of the polymer network, appropriate filler selection, and controlled cure kinetics design, the cure shrinkage and warpage were significantly reduced over other designs. Furthermore, the low warpage stability of the molded wafer is maintained through post-mold curing, PI simulation, and RDL simulation process steps ultimately leading to improved reliability performance. Compared to traditional anhydride-based LCM, our reliability data (after 96 hours of uHAST & 1000 cycles of AATC) clearly indicates performance advantages of no filler-fall-off, no delamination, and better chemical resistance. In terms of workability, the new system shows improved work-life, fast-cure at 110–130°C, and complete gap filling. Lower die shift, good mold release, and improved tape debonding has also been observed through formulation and process optimization. Taking advantage of the proprietary resin and formulation design, Henkel's new LCM materials are delivering positive results in new FO-WLP designs and WLCSP applications needing 5-side or 6-side protection.

Material Design Advancement Create Multifunctional Materials for Single-Layer Bonding and Debonding

Multifunctional materials are a relatively new topic in the semiconductor industry for wafer-level packaging (WLP). With the increase in processing steps and the emergence of more advanced technologies, the use of multifunctional materials will become a more integral part in the future of temporary bonding and debonding (TB/DB) as well as other advanced packaging applications. One approach to multifunctional material design incorporates adhesive and laser release attributes in one material layer. Although this is similar to a thermal release material, it has greater thermal capabilities due to its ability to be cured and undergo laser debond. Many advantages may be obtained by combining a curable adhesive and laser release layer into one material. One of the greatest advantages is the reduction in overall processing time and steps required to bond wafer pairs as well as the reduction of chemical waste, due to the use of one material compared to two or more materials which significantly reduces the cost of ownership. Curable adhesive single layer systems offer access to higher temperatures with less material flow from the curable layer, strong adhesion for high stress applications where wafers can delaminate or spontaneously debond when using multilayer mechanically debonding systems such as Fan-Out Wafer Level Packaging (FOWLP), and offer lower wafer stress and warpage due to fewer material interfaces within the bonded wafer pairs causing less potential mismatch of materials coefficient of thermal expansion(CTE). Some challenges with this concept stem from the concern of the cleanability of a curable layer and potential laser damage to the device. In order to wet clean a curable layer, which is usually very solvent resistant due to the crosslinked nature, requires harsh solvent based solutions (that may contain either strong acid or base, require long cleaning time, and high temperature). This study will address all of the aforementioned challenges and includes the developmental advancements in material designs that resulted in the creation of new multifunctional materials. These multifunctional materials have been designed to be thermally curable, prevent material reflow of the bonding layer at higher temperatures, while still remaining wet cleanable without the use of harsh chemicals and long times. As with any material that utilize laser release methods there are concerns about device damage from laser energy penetrating to the device but multifunctional materials address this in two ways: they offer high absorbance of the laser energy at all commercially available laser tool wavelengths and they can be utilized as a thicker film as they act as the bonding layer as well. By overcoming their challenges, they will minimize the cost of ownership while driving advancement in future materials and processing.

Cost Comparison of Panel Level and Wafer Level Fan-out Packaging

In recent years, the possibility of panels replacing wafers in some fan-out applications has been a topic of interest. Questions of cost and yield continue to arise even as the industry appears to be full steam ahead. While large panels allow for more packages to be produced at once, the cost does not scale simply based on how many more packages can be generated from a panel over a wafer. This analysis begins by breaking down the types of cost and will discuss how those types of cost are impacted (or not) by the shift from wafer to panel. Activity based cost modeling is used; this is a detailed, bottom-up approach that takes into account each type of cost for each activity in a process flow. Two complete cost models were constructed for this analysis. A variety of package sizes are analyzed, and multiple panel sizes are included as well. For each set of activities in the fan-out process flow, there is an explanation of how the process changes with the move to panel, including assumptions related to throughput, equipment price, and materials. The cost reduction that may be achieved at each package and panel size will be presented for each processing segment. The focus of this analysis is on the details of each segment of the process flow, but results for the total cost of various packages will also be presented. There is also a section of analysis related to the impact of yield on the competitiveness of panel processing.

A Numerical Study on Mitigation of Flying Dies in Compression Molding of Microelectronic Packages

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dice during encapsulation in fan-out wafer-level packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemorheology, and to extract forces exerted on individual dice. It offers separate evaluation of pressure and shear contributions for two cases, 0° and 45° between the dice' frontal area and the melt front. Process parameters, such as compression speed, thus cycle time, and process temperature, are determined to keep the forces on the dice below the critical level, where drag forces exceed adhesive forces. As a result, process parameters are determined to minimize flying dice and thereby maximize yield. The approach is easily transferable to arbitrary geometries and is therefore well suited to face the challenges that come with the current efforts toward the transition from FOWLP to larger substrates.

An Electromagnetic Bandgap Structure Integrated With RF LNA Using Integrated Fan-Out Wafer-Level Package for Gigahertz Noise Suppression

This paper presents a periodic electromagnetic bandgap (EBG) structure in the integrated fan-out wafer-level package (InFO-WLP) technology for gigahertz-band noise suppression. The proposed EBG structure consists of an $LC$ resonator with two symmetrical spiral inductors in series and a shunt metal–insulator–metal capacitor between power and ground planes. The third-order equivalent model of the EBG structure is also proposed and extracted by field solver ANSYS Q3D to model the performance. In addition, the EBG arrays with different sizes of unit cell and the corresponding stopband bandwidth and isolation were characterized. The measurement results show that the proposed $1 \times 4$ EBG array of 600- $\mu \text{m}$ square unit cell can achieve a 29.5-GHz stopband bandwidth together with an over 30-dB isolation level. Furthermore, by using the InFO-WLP technology, the proposed EBG structure is integrated with an RF low-noise amplifier (LNA) fabricated in a 16-nm FinFET technology as a case study to validate the power noise immunity. The experimental results show that the measured output spectrum of LNA integrated with the proposed EBG structure at the power plane can suppress the noise tone from −37.37 to −68.65 dBm.

Advanced Packaging Fault Isolation Case Studies and Advancement of EOTPR

Abstract Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

A study of Sub-micron Fan-out Wafer Level Packaging solutions

Abstract In Fan-out Wafer Level Packaging (FOWLP) processes, redistribution layer (RDL) line width reduction is a key challenge to expand the FOWLP market to multi-chip interconnections, including interconnections between SoC and DRAM, split-die connection of FPGA, and interconnections between image sensors and SoC. Next generation FOWLP requires 1.0 μm RDL and future FOWLP is targeting 0.8 μm RDL. To meet these requirements, Canon has developed new projection optics with a high NA and wide-field that is best suited for sub-micron FOWLP. These projection optics are a new option for FPA-5520iV steppers, offering NA 0.24 imaging and a 52 × 34 mm exposure field. FPA-5520iV steppers with NA 0.24 provide excellent 0.8 μm resolution performance throughout all imaging fields thanks to Canon's wave-front aberration based projection optics manufacturing methods and on-axis optical tilt focus sensor.

Advances in Temporary Bonding and Debonding Technologies for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP) Processes

AbstractToday's complex fan-out wafer-level packaging (FOWLP) processes include the use of redistribution layers (RDL) and reconstituted wafers with epoxy mold compound (EMC) for use in heterogeneous integration [1]. Wafer-level system-in-package (WLSiP) uses fan-out wafer-level packaging (FOWLP) to build the system-in-package (SiP) by attaching know-good die (KGD) in a chip-first process to a tape laminated temporary carrier. If the dies are attached in a die-up configuration (active area facing up) and then over-molded with EMC, contact pads on the embedded die are exposed during the backside grind process. During the RDL build, the temporary carrier supplies mechanical support for the thinned substrate. In a die-down configuration with the active area facing down (eWLB), the temporary carrier is removed after the molding process thus exposing the contact pads for RDL build and solder ball mount.The ideal chip attachment scheme should minimize lateral movement of the die during over-mold (die shift) and also minimize vertical deformation of the bonding material. Thermal release tape provides a convenient way to attach die to a carrier prior to over-molding with EMC. However, not all bonding materials are suitable for presentation in tape form, so the material used in the tape may not be the optimal choice. An alternative method is to directly apply temporary bonding material to the carrier substrate. This enables the use of bonding materials with higher melt viscosity and improved thermal stability, resulting in less vertical deformation during die placement, and reduced die shift during over-molding. The bonding material will ideally have high adhesion to the EMC wafer to prevent delamination in the bond line during downstream processing. Stack stress and warpage is a major concern which causes handling and alignment problems during processing. The bonding material and carrier will need to be specifically suited to minimize the effects of stress in the compound wafer.Such material must balance rigidity with warp to prevent lateral die shift and deformation induced by coefficient of thermal expansion (CTE) mismatch between the carrier and EMC material [2]. Bonding materials must also have enough adhesion to the EMC material to overcome such stress without bond failure for an associated debond path (such as laser or mechanical release). In this experiment, we will examine a thermoplastic bonding material in combination with different release materials, addressing die shift, and deformation after EMC processing. Successful pairs will then undergo carrier release using either mechanical release or laser ablation release technology.

Novel Low Temperature Curable Photosensitive Negative-tone Polyimide with Higher Resolution and Reliability

Abstract Hitachi Chemical DuPont MicroSystems (HDMS) has been developing photo sensitive negative-tone polyimides (PIs) as dielectrics for re-distribution layers (RDLs) in wafer level packages (WLPs) and as protection layers in semiconductor ICs. Photo sensitive negative-tone PIs can simplify the manufacturing process and ensure high reliability owing to their good mechanical properties, high thermal stability, and high electrical properties. On the other hand, since advanced packaging application such as Fan-Out WLP (FO-WLP) requires finer L/S design as well as higher reliability, lithographic performance of PIs has to be further improved and good cured film property should be achieved when cured at lower temperature (<230 °C). In order to meet these requirements, HDMS started the development of new PI which shows enhanced lithographic performance with good film property. In this paper, we will demonstrate our novel low temperature curable photo sensitive solvent developable negative-tone PI. By adopting a new photo-package to improve lithographic performance, this PI can achieve 3 μm via opening at 5 μm cured thickness and 5 μm via opening at 10 μm cured thickness with smooth pattern profile after cure. In addition, this PI shows good film property when cured at 200 °C and no electrical failure is observed during 300h bias-HAST using 2/2 μm L/S pattern.

Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost

Abstract Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements. In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates. The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.

Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation

Abstract Physical Vapor Deposition (PVD) systems are widely used in the semiconductor fabrication industry, both for front-end applications in the wafer fab and for back-end applications at device packaging houses. In fan-out wafer level packaging (FOWLP), and in fan-out panel level packaging (FOPLP), sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built. For these RDL barrier/seed layers, PVD cluster tools, wafer transport architectures that have been widely used since the mid-1980s, are the current Process of Record (POR) in advanced packaging; however, these tools typically operate in a regime where wafer transport is robot-limited to approximately 50 wafers per hour, which limits overall throughput and greatly influences Cost of Ownership (COO) for the sputter deposition step(s), because the central handling robot occupied with a transfer from the Ti PVD module to the Cu PVD module, for example, has no opportunity to be doing anything other than that specific transfer. Other wafer transport architectures are more efficient from a wafer handling perspective. In linear transport carrier-based PVD tools, wafers or panels passing through the system benefit from a mechanical transfer time budget that is considerably less than for a cluster tool. Transport time overhead per wafer on linear transport systems is quite low, and scheduler software optimization becomes less onerous too, as a result of the simpler wafer transport architecture. We analyzed the relative throughput of cluster and linear transport PVD tools for a typical FOWLP barrier/seed layer (1000Å Ti / 2000Å Cu) sputter deposition process, and present details here of how the time spent moving wafers to various processing chambers affects overall system productivity. In the case of the cluster tool architecture, with its central wafer handling robot, wafer throughputs are approximately 50 wafers per hour, while on the linear transport system wafer throughputs as high as 240 wafers per hour are possible. The significant difference in system throughputs greatly affects the relative Cost of Ownership (COO) per wafer processed, with the linear transport system returning COO results that are less than half those of the typical cluster PVD tool.

Optical Run-Out Correction for Improved Lithography Overlay Accuracy for FOWLP Applications

Abstract Finer features sizes in advanced Wafer-level-packaging (WLP) processes create increasing demands to improve lithography equipment overlay control. The improvement goes beyond the inherent overlay capability of the equipment (“tool-to-itself”), but requires ways to compensate for mismatches in actual feature size and position on the wafer with respect to the photomask pattern. In Fan-Out wafer level packaging (FOWLP), error contributions from the die placement robot, and especially errors from expanding and shrinking mold compound in which the dies are embedded (magnification error), lead to undesirable errors in layer to layer overlay. Mask-less laser direct imaging (LDI) technologies or die-by-die alignment strategies on steppers can deal with these error contributions, but they cannot provide adequate throughput and have a high cost-of-ownership, and therefore offer a limited solution for the industry. An Active Optical Magnification Correction and Beam-Steering technology option has been developed, available on a full-field UV projection scanner tool. This option allows compensating any type of run-out or run-in up to +/− 200 ppm, or die shifts of +/− 30 μm on a 300 mm wafer, which corresponds to the amount of magnification error caused by the embedding of dies in mold compound nowadays. In addition, an additional optical asymmetrical correction function has been developed to compensate shifts of up to 50ppm in either X or Y. This paper will detail the principle and realization of this optical magnification correction technology. Performance data results for magnification error mitigation will be presented, and its effects on overlay, patterning performance, resolution, and throughput will be studied.

A numerical study on mitigation of flying dies in compression molding of microelectronic packages

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front. Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield. The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.