Design and Optimization of Wafer-Level Compression Molding Process for One Chip Plus Multiple Decaps

Abstract

Decaps are the panacea for the noise-related issues. Due to the short distance advantage, decaps are embedded in the fan-out wafer-level package instead of the printed circuit board. These decaps, generally thicker than chips, will have a crucial influence on the molding process as well. A lot of issues are encountered in the molding process, especially with lots of decaps, i.e., voids issues, incomplete filling issues, and die shift issues. In an optimized design, all these issues should be prevented or reduced as much as possible. In this paper, design flow for the wafer-level molding process is demonstrated and design guidelines are provided. Three important evaluation standards are used to evaluate the design, i.e., incomplete filling, drag force, and voids. Two kinds of design parameters, structure parameters (i.e., die placement, die size and thickness, and so on) and process parameters (i.e., vacuum pressure, filling speed, and so on), are optimized in the whole study. Optimization of these parameters helps the real wafer-level molding process to be conducted smoothly.