Warpage Prediction and Experiments of Fan-Out Waferlevel Package During Encapsulation Process

Abstract

A wafer level package (WLP) that has a flip chip form and uses thin-film redistribution with solder bumps to connect the package to the printed wiring board directly is discussed in this paper. A liquid molding compound is used for the encapsulation process. Since the thickness of the fan-out WLP is smaller than that in a traditional integrated circuit (IC) package, the fan-out WLP induces more serious warpage. Warpage plays an important role during the IC encapsulation process, and too large a warpage would not let the package proceed to the next manufacturing process. This paper uses an approach that considers both cure- and thermal-induced shrinkages during the encapsulation process to predict the amount of warpage. Cure-induced shrinkage is described by the pressure-volume-temperature-cure (PVTC) equation of the liquid compound. The thermally induced shrinkage is described by the coefficients of thermal expansion of the component materials. The liquid compound properties are obtained by various techniques, such as cure kinetics by differential scanning calorimetry- and cure-induced shrinkage by a PVTC testing machine. These experimental data are used to formulate the PVTC equation. A fan-out WLP is first simulated, and the simulation results are verified with experiments. It is shown that an approach that considers both thermal and cure/compressibility effects can better predict the amount of warpage for the fan-out WLP. The PVTC equation is successfully implemented, and it is verified that warpage is governed by both thermal and cure shrinkages. The amount of warpage after molding could be accurately predicted with this methodology. Simulation results show that cure shrinkage of the liquid compound is the dominant factor responsible for package warpage after encapsulation.