Crossbar Architecture Research Articles

Improvement of forming-free threshold switching reliability of CeO2-based selector device by controlling volatile filament formation behaviors

Diffusive memristor-based threshold switching devices are promising candidates for selectors in the crossbar memory architecture. However, the reliability and uniformity of the devices are primary concerns due to uncontrolled diffusion of metal ions in the solid electrolyte of diffusive memristors. In this study, CeO2-based selectors with Ag electrodes were demonstrated to have forming-free threshold switching characteristics. In particular, by inserting an amorphous SiO2 layer in a CeO2-based selector device, we have effectively controlled volatile filament formation that is essential for uniform and reliable switching operations. The inserted SiO2 layer acts as a barrier that could retard the migration of Ag ions and prevents the formation of strong filaments in the solid electrolyte. This enables the bilayer device to have improved uniformity and cyclic endurance. The proposed selector device, Ag/CeO2/SiO2/Pt, showed excellent DC I–V switching cycles (103), high selectivity of 104, good endurance (>104), and narrow distribution of switching voltages. These results would be helpful to implement CeO2-based threshold switching devices as selectors for high-density storage crossbar memory architectures.

Analyzing the Impact of Memristor Variability on Crossbar Implementation of Regression Algorithms With Smart Weight Update Pulsing Techniques

This paper presents an extensive study of linear and logistic regression algorithms implemented with 1T1R memristor crossbars arrays. Using a sophisticated simulation platform that wraps circuit-level simulations of 1T1R crossbars and physics-based models of RRAM (memristors), we elucidate the impact of device variability on algorithm accuracy, convergence rate and precision. Moreover, a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">smart pulsing strategy</i> is proposed for practical implementation of synaptic weight updates that can accelerate training in real crossbar architectures. Stochastic multi-variable linear regression shows robustness to memristor variability in terms of prediction accuracy but reveals impact on convergence rate and precision. Similarly, the stochastic logistic regression crossbar implementation reveals immunity to memristor variability as determined by negligible effects on image classification accuracy but indicates an impact on training performance manifested as reduced convergence rate and degraded precision.

Tunable lanthanum doping in double perovskite films for read-only memory

Rare earth ions have been widely investigated as active dopants in various materials because of their distinct optical, electronic and magnetic properties. Halide perovskite resistive memories have attracted increasingly recent interest for tremendous potential applications in computation and data storage techniques. However, it remains unexplored to implement rare earth doping strategy for tuning perovskite resistive memories. Here, we report read-only memories based on environment-friendly and air-stable lead-free double perovskite Cs2AgBiBr6 films, which is particularly tuned by rare earth La3+ doping. We use the vacuum sublimation and solution processing method to obtain Cs2AgBiBr6 crystals doped by different content La3+, and fabricate resistive memory devices based on doped Cs2AgBiBr6 films. The simplest sandwich-like structure composed of ITO/La-doped-Cs2AgBiBr6/Ag only is designed in cross-bar array architecture with high-integration and simple operation. The resistive memory device of La-doped Cs2AgBiBr6 films demonstrate a typical write-once-read-many-times (WORM) behavior with low onset voltage of 1 V and long retention time of 12000 s. In particular, the ON/OFF ratio of the La-doped Cs2AgBiBr6 film is 100 times higher than that of the undoped Cs2AgBiBr6 film. This study provides a new insight to design and manipulate memory devices based on lead-free halide perovskite materials through doping effect of rare earth ions.

Constrained Coding and Deep Learning Aided Threshold Detection for Resistive Memories

Resistive random access memory (ReRAM) is a promising emerging non-volatile memory (NVM) technology that shows high potential for both data storage and computing. However, its crossbar array architecture leads to the sneak path (SP) problem, which may severely degrade the data storage reliability of ReRAM. Due to the complicated nature of the SP-induced interference (SPI) <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> , it is difficult to derive an accurate channel model for it. The deep learning (DL)-based detection scheme (Zhong <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> , 2020) can better mitigate the SPI, at the cost of additional power consumption and read latency. In this letter, we first propose a novel constrained coding (CC) scheme which can not only reduce the SPI, but also effectively differentiate the memory arrays into two categories of SPI-free and SPI-affected arrays. For the SPI-free arrays, we can use a simple middle-point threshold detector to detect the low and high resistance cells of ReRAM. For the SPI-affected arrays, a DL detector is first trained off-line. To avoid the additional power consumption and latency introduced by the DL detector, we further propose a DL-based threshold detector, whose detection threshold can be derived based on the outputs of the DL detector. It is then utilized for the online data detection of all the identified SPI-affected arrays. Simulation results demonstrate that the above CC and DL aided threshold detection scheme can effectively mitigate the SPI of the ReRAM array and achieve better error rate performance than the prior art detection schemes, without the prior knowledge of the channel.

CoMIC: Complementary Memristor based in-memory computing in 3D architecture

The use of memristors, also known as Resistive Random Access Memory (ReRAM), has been widely investigated in recent years for non-volatile memory design applications. Memristors can also be used for realizing logic operations, leading to new in-memory computing (IMC) architectures. However, the presence of sneak paths in crossbar arrays limits the practical use of such systems. In this paper, we introduce a novel sneak path-free ReRAM system capable of both memory and logic operations using Complementary Resistive Switches (CRS) or Complementary Memristors (CMs) crossbar array. CMs can mitigate the effect of sneak paths and are good candidates for realizing three-dimensional memory array. A novel IMC-enabled two-dimensional (2D) and three-dimensional (3D) crossbar architecture have been proposed. The devices are modeled using the VTEAM memristor model and can perform majority (MAJ) gate operations directly on the crossbar. A logic mapping approach is also proposed, allowing serial and parallel evaluation of MAJ operations for given high-level logic functions. The efficacy of the approach has been evaluated by estimating the computation cycles, crossbar size, delay, and energy for various benchmark functions. The results show that the proposed method yields up to 91.19% improvement over an existing IMC method in computation steps and 78.90% reduction in terms of the number of memristors required.

Connectome of memristive nanowire networks through graph theory

Hardware implementation of neural networks represents a milestone for exploiting the advantages of neuromorphic-type data processing and for making use of the inherent parallelism associated with such structures. In this context, memristive devices with their analogue functionalities are called to be promising building blocks for the hardware realization of artificial neural networks. As an alternative to conventional crossbar architectures where memristive devices are organized with a top-down approach in a grid-like fashion, neuromorphic-type data processing and computing capabilities have been explored in networks realized according to the principle of self-organization similarity found in biological neural networks. Here, we explore structural and functional connectivity of self-organized memristive nanowire (NW) networks within the theoretical framework of graph theory. While graph metrics reveal the link of the graph theoretical approach with geometrical considerations, results show that the interplay between network structure and its capacity to transmit information is related to a phase transition process consistent with percolation theory. Also the concept of memristive distance is introduced to investigate activation patterns and the dynamic evolution of the information flow across the network represented as a memristive graph. In agreement with experimental results, the emergent short-term dynamics reveals the formation of self-selected pathways with enhanced transport characteristics connecting stimulated areas and regulating the trafficking of the information flow. The network capability to process spatio-temporal input signals can be exploited for the implementation of unconventional computing paradigms in memristive graphs that take into advantage the inherent relationship between structure and functionality as in biological systems.

Resistive switching properties for fluorine doped titania fabricated using atomic layer deposition

This study demonstrates a new resistive switching material, F-doped TiO2 (F:TiO2), fabricated by atomic layer deposition (ALD) with an in-house fluorine source for resistive random access memory (RRAM) devices. Controlling oxygen vacancies is required since RRAM uses resistive switching (RS) characteristics by redistributing oxygen ions in oxide, and poor oxygen defect control has been shown to significantly reduce RRAM reliability. Therefore, this study designed an F based RRAM device using fluorine anions rather than oxygen defect for the main agent of RS behavior. We developed the F:TiO2 RRAM material using a novel in situ doping method in ALD and investigated its RS behaviors. The Pt/F:TiO2/Pt device exhibited forming-less bipolar RS and self-rectifying behavior by fluorine anion migration, effectively reducing the sneak current in crossbar array architecture RRAM. The doped fluorine passivated and reduced oxygen related defects in TiO2, confirmed by x-ray photoelectron spectroscopy analysis. Adopting the F-based RS material by ALD provides a viable candidate for high reliability RRAM.

All-Electrical Control of Compact SOT-MRAM: Toward Highly Efficient and Reliable Non-Volatile In-Memory Computing.

Two-dimensional van der Waals (2D vdW) ferromagnets possess outstanding scalability, controllable ferromagnetism, and out-of-plane anisotropy, enabling the compact spintronics-based non-volatile in-memory computing (nv-IMC) that promises to tackle the memory wall bottleneck issue. Here, by employing the intriguing room-temperature ferromagnetic characteristics of emerging 2D Fe3GeTe2 with the dissimilar electronic structure of the two spin-conducting channels, we report on a new type of non-volatile spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device based on Fe3GeTe2/MgO/Fe3GeTe2 heterostructure, which demonstrates the uni-polar and high-speed field-free magnetization switching by adjusting the ratio of field-like torque to damping-like torque coefficient in the free layer. Compared to the conventional 2T1M structure, the developed 3-transistor-2-MTJ (3T2M) cell is implemented with the complementary data storage feature and the enhanced sensing margin of 201.4% (from 271.7 mV to 547.2 mV) and 276% (from 188.2 mV to 520 mV) for reading “1” and “0”, respectively. Moreover, superior to the traditional CoFeB-based MTJ memory cell counterpart, the 3T2M crossbar array architecture can be executed for AND/NAND, OR/NOR Boolean logic operation with a fast latency of 24 ps and ultra-low power consumption of 2.47 fJ/bit. Such device to architecture design with elaborated micro-magnetic and circuit-level simulation results shows great potential for realizing high-performance 2D material-based compact SOT magnetic random-access memory, facilitating new applications of highly reliable and energy-efficient nv-IMC.

Modeling and design of a Mott selector for a ReRAM-based non-volatile memory cell in a crossbar architecture

In this work, we developed a model for a nonvolatile memory cell based on the electrical model for a TiOX/HfOx ReRAM cell and the hybrid electrothermal model of a VO2 Mott selector developed recently by our team. Both models have been calibrated and validated with experimental data, and the operating characteristics of a one-selector-one-ReRAM (1S1R) memory cell has been studied. The length of the selector layer was varied as a design parameter to meet the design requirements for proper read, write, and erase operations. Simulation results suggest that the modified selector cell with 60 nm length of the VO2 layer meets all the requirements for proper operation, with a cell write voltage of 1.6 V and erase voltage of 2.5 V. The access time for this structure was studied by benchmarking with experimental data. Write access time of 10.5 ns and erase access time of 16 ns have been obtained from simulations.

Arrays of Nanocomposite Crossbar Memristors for the Implementation of Formal and Spiking Neuromorphic Systems

Memristors are promising devices for use as synapses in hardware-based artificial formal and spiking neural networks. Their use can increase the energy efficiency of such networks when solving various cognitive tasks. At the same time, for the implementation of hardware-based neural networks, a large number of rather densely packed structures are required, which can be achieved by creating memristive matrices in a crossbar architecture. Crossbar arrays of nanocomposite memristors on silicon substrates with protection against edge effects are developed and manufactured, their resistive switching is investigated, a formal neural network is created on their basis, which is capable of recognizing simple patterns after loading a pretrained weight map, and the possibility of precise adjustment of the conductivity of the crossbar memristors by various means applicable in the creation of more complex spiking and formal neural networks is demonstrated.

Linear and Symmetric Li-Based Composite Memristors for Efficient Supervised Learning.

Emerging energy-efficient neuromorphic circuits are based on hardware implementation of artificial neural networks (ANNs) that employ the biomimetic functions of memristors. Specifically, crossbar array memristive architectures are able to perform ANN vector-matrix multiplication more efficiently than conventional CMOS hardware. Memristors with specific characteristics, such as ohmic behavior in all resistance states in addition to symmetric and linear long-term potentiation/depression (LTP/LTD), are required in order to fully realize these benefits. Here, we demonstrate a Li-based composite memristor (LCM) that achieves these objectives. The LCM consists of three phases: Li-doped TiO2 as a Li reservoir, Li4Ti5O12 as the insulating phase, and Li7Ti5O12 as the metallic phase, where resistive switching correlates with the change in the relative fraction of the metallic and insulating phases. The LCM exhibits a symmetric and gradual resistive switching behavior for both set and reset operations during a full bias sweep cycle. This symmetric and linear weight update is uniquely enabled by the symmetric bidirectional migration of Li ions, which leads to gradual changes in the relative fraction of the metallic phase in the film. The optimized LCM in ANN simulation showed that exceptionally high accuracy in image classification is realized in fewer training steps compared to the nonlinear behavior of conventional memristors.

Early Design Space Exploration Framework for Memristive Crossbar Arrays

For memristive crossbar arrays, currently, no high-level design validation and early space exploration tools exist in the literature. Such tools are essential to quickly verify the design functionality as well as compare design alternatives in terms of power and performance. In this work, we propose a VHDL-based framework that enables us to quickly perform behavioral simulation as well as estimate dynamic energy consumption and speed of any large memristive crossbar array. We propose a high-level (VHDL) model of a memristor based on which crossbar architectures can be modeled. The individual memristor model is embedded with power and delay numbers obtained from a detailed memristor model. We demonstrate the framework for MAGIC-style memristive crossbars. We validate the framework against detailed Verilog-A based model on fifteen combinational benchmarks. For the single row model, we obtained 153x simulation speedup over HSPICE, average estimation errors of 6.64% and 0% for dynamic energy consumption and cycle-time, respectively. For the transpose model, we obtained average estimation errors of 5.51% and 10.90% for dynamic energy consumption and cycle-time, respectively. We also extend our framework to support another prominent logic style and validate through a case study. The proposed framework can be easily extended to other emerging technologies.

Improved Crossbar Array Architecture for Compensating Interconnection Resistance: Ferroelectric HZO-Based Synapse Case

In-memory computing is a promising solution to break through the conventional von Neumann bottleneck. Owing to the low-power consumption, Si fabrication compatibility and fast switching speed, the HfZrOx (HZO)-based ferroelectric devices attract attention as artificial synapses. By using crossbar architectures, artificial synapse array can greatly speed up the efficiency for neuromorphic applications. However, interconnect resistance effect will cause a serious decrease in calculation accuracy. This paper proposes a crossbar array architecture with the HZO-based ferroelectric synapses, which can restore the current distortion caused by the interconnect resistance. At the device level, the synaptic potentiation and depression behaviors are achieved by adjusting the pulse duration. For the circuit level, the interconnect resistance can be significantly compensated. In neuromorphic computing, a high accuracy rate of 96% is realized, which can be further improved with the expansion of the array size. Our results provide a step towards the development of large-scale ferroelectric HZO-based neuromorphic devices.

Local anodic oxidation of silicon for create crossbar architecture

Paper present possibility of creation a neuromatrix in the form crossbar architecture on a silicon substrate is shown. Crossbar architecture in the form of a set of nanosized conductors, between which there is a layer of titanium oxide, capable of changing its conductivity under the action of the applied voltage, it is proposed to form using the method of local anodic oxidation. The results is present of the study technological parameters of the method of local anodic oxidation silicon and titanium for the implementation of the elements of this neuromatrix in the form of a memristor structures. Keywords: Silicon, titanium, local anodic oxidation, neuromatrix, crossbar.

Локальное анодное окисление кремния для создания кроссбар-архитектуры

Paper present possibility of creation a neuromatrix in the form crossbar architecture on a silicon substrate is shown. Crossbar architecture in the form of a set of nanosized conductors, between which there is a layer of titanium oxide, capable of changing its conductivity under the action of the applied voltage, it is proposed to form using the method of local anodic oxidation. The results is present of the study technological parameters of the method of local anodic oxidation silicon and titanium for the implementation of the elements of this neuromatrix in the form of a memristor structures.

Design and Simulation of Ring Network-on-Chip for Different Configured Nodes

The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. Ring (Octagons) is a direct NoC that is specifically used to solve the scalability problem by expanding each node in the shape of an octagon. This paper discusses the ring NoC design concept and its simulation in Xilinx ISE 14.7, as well as the communication of functional nodes. For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. The design allows 64 to 256 node communication in a single chip with ‘N’ bit data transfer in the ring NoC. The performance of the NoC is evaluated with variable nodes from 2 to 256 in Digilent manufactured Virtex-5 FPGA hardware.

Analysis of Parasitic Effects in a Crossbar in CMOS Based Neuromorphic System for Pattern Recognition Using Memristive Synapses

This paper proposes a complete CMOS realized neuromorphic system for pattern recognition having CMOS-based memristor emulators as synaptic circuits. The crossbar array of the system is modeled by considering the emulator circuit&#x0027;s area to determine the spacing between the interconnects. The interconnect parasitics are obtained from the ANSYS Q3D extractor. Parasitics extracted are also validated using the analytical model. A crossbar array architecture modeled with the extracted parasitic components and the memristor emulator will provide an understanding of the behavior of the crossbar array and can be used to analyze the parasitic effects on various real-time applications. Our analysis shows that as the operating frequency increases, the recognition rate of the neuromorphic system is reduced by 66.67&#x0025; due to the crossbar&#x0027;s parasitics, non-idealities of the neuron, and memristor circuits. The memristor&#x0027;s state, either low or high resistance, significantly affects the system&#x0027;s performance, which is evaluated by the rise time and signal delay. The energy consumed by the CMOS-based memristor emulator synapse for recognizing each pattern is 0.44 &#x00A0;<inline-formula><tex-math notation="LaTeX">$nJ$</tex-math></inline-formula>, which is significantly lower when compared with the previous works. The circuit design and verification are done using 180-nm CMOS technology.

Electroforming-free threshold switching of NbO x -based selector devices by controlling conducting phases in the NbO x layer for the application to crossbar array architectures.

Bipolar threshold switching characteristics, featuring volatile transition between the high-resistance state (HRS) at lower voltage than threshold voltage (Vth) and the low-resistance state (LRS) at higher voltage irrespective of the voltage polarity, are investigated in the Nb(O)/NbOx/Nb(O) devices with respect to deposition and post-annealing conditions of NbOx layers. The device with NbOx deposited by reactive sputtering with 12% of O2 gas mixed in Ar shows threshold switching behaviors after electroforming operation at around +4 V of forming voltage (Vf). On the other hand, electroforming-free threshold switching is achieved from the device with NbOx deposited in the reduced fraction of 7% of O2 gas and subsequently annealed at 250 °C in vacuum, thanks to the increase of the amount of conducting phases within the NbOx layer. Threshold switching is thought to be driven by the formation of a temporally percolated filament composed of conducting NbO and NbO2 phases in the NbOx layer, which were formed as a result of the interaction with Nb electrodes such as oxygen ion migration either by annealing or electrical biasing. The presence of a substantial amount of oxygen in the Nb electrodes up to ∼40 at%, named Nb(O) herein, would alleviate excessive migration of oxygen and consequent overgrowth of the filament during operation, thus enabling reliable threshold switching. These results demonstrate a viable route to realize electroforming-free threshold switching in the Nb(O)/NbOx/Nb(O) devices by controlling the contents of conducting phases in the NbOx layer for the application to selector devices in high-density crossbar memory and synapse array architectures.

Rotaxane nanomachines in future molecular electronics.

As the electronics industry is integrating more and more new molecules to utilize them in logic circuits and memories to achieve ultra-high efficiency and device density, many organic structures emerged as promising candidates either in conjunction with or as an alternative to conventional semiconducting materials such as but not limited to silicon. Owing to rotaxane's mechanically interlocked molecular structure consisting of a dumbbell-shaped molecule threaded through a macrocycle, they could be excellent nanomachines in molecular switches and memory applications. As a nanomachine, the macrocycle of rotaxane can move reversibly between two stations along its axis under external stimuli, resulting in two stable molecular configurations known as “ON” and “OFF” states of the controllable switch with distinct resistance. There are excellent reports on rotaxane's structure, properties, and function relationship and its application to molecular electronics (Ogino, et al., 1984; Wu, et al., 1991; Bissell, et al., 1994; Collier, et al., 1999; Pease, et al., 2001; Chen, et al., 2003; Green, et al., 2007; Jia, et al., 2016). This comprehensive review summarizes [2]rotaxane and its application to molecular electronics. This review sorts the major research work into a multi-level pyramid structure and presents the challenges of [2]rotaxane's application to molecular electronics at three levels in developing molecular circuits and systems. First, we investigate [2]rotaxane's electrical characteristics with different driving methods and discuss the design considerations and roles based on voltage-driven [2]rotaxane switches that promise the best performance and compatibility with existing solid-state circuits. Second, we examine the solutions for integrating [2]rotaxane molecules into circuits and the limitations learned from these devices keep [2]rotaxane active as a molecular switch. Finally, applying a sandwiched crossbar structure and architecture to [2]rotaxane circuits reduces the fabrication difficulty and extends the possibility of reprogrammable [2]rotaxane arrays, especially at a system level, which eventually promotes the further realization of [2]rotaxane circuits.

Memristor based spiking neural network accelerator architecture

Spiking neural network (SNN) as the third-generation artificial neural network, has higher computational efficiency, lower resource overhead and higher biological rationality. It shows greater potential applications in audio and image processing. With the traditional method, the adder is used to add the membrane potential, which has low efficiency, high resource overhead and low level of integration. In this work, we propose a spiking neural network inference accelerator with higher integration and computational efficiency. Resistive random access memory (RRAM or memristor) is an emerging storage technology, in which resistance varies with voltage. It can be used to build a crossbar architecture to simulate matrix computing, and it has been widely used in processing in memory (PIM), neural network computing, and other fields. In this work, we design a weight storage matrix and peripheral circuit to simulate the leaky integrate and fire (LIF) neuron based on the memristor array. And we propose an SNN hardware inference accelerator, which integrates 24k neurons and 192M synapses with 0.75k memristor. We deploy a three-layer fully connected network on the accelerator and use it to execute the inference task of the MNIST dataset. The result shows that the accelerator can achieve 148.2 frames/s and 96.4% accuracy at a frequency of 50 MHz.