Crossbar Architecture Research Articles

Non‐Volatile Hybrid Optical Phase Shifter Driven by a Ferroelectric Transistor

AbstractOptical phase shifters are essential elements in photonic integrated circuits (PICs) and function as a direct interface to program the PICs. Non‐volatile phase shifters, which can retain information without a power supply, are highly desirable for low‐power static operations. Here a non‐volatile optical phase shifter is demonstrated by driving a III‐V/Si hybrid metal‐oxide‐semiconductor (MOS) phase shifter with a ferroelectric field‐effect transistor (FeFET) operating in the source follower mode. Owing to the various polarization states in the FeFET, multistate non‐volatile phase shifts up to 1.25π are obtained with CMOS‐compatible operation voltages and low switching energy up to 3.3 nJ. Furthermore, a crossbar array architecture is proposed to simplify the control of non‐volatile phase shifters in large‐scale PICs and verify its feasibility by confirming the selective write‐in operation of a targeted FeFET with a negligible disturbance to the others. This work paves the way for realizing large‐scale non‐volatile programmable PICs for emerging computing applications such as deep learning and quantum computing.

Analyzing the impact of parasitics on a CMOS-Memristive crossbar neural network based on winner-take-all and Hebbian rule

For cognitive tasks and classifications, neuromorphic systems have shown great potential. This paper presents a novel architecture using CMOS memristive synapses where the memristors are trained using the Hebbian rule, and the winner-take-all mechanism is used for the recognition task. The proposed architecture offers a simplified approach compared to previous state-of-the-art works, making it accessible for implementing pattern recognition tasks with in-memory computation. As the size of the memristive switching devices is in the nanometer scale, designing, modeling, and optimizing the system becomes increasingly complex. This complexity leads to various signal integrity issues that arise due to parasitic components of the crossbar. A crossbar array architecture is designed using the extracted crossbar’s parasitic components obtained using the Q3D extractor. The modeled architecture provides insight into the crossbar array’s parasitic affect behavior at the schematic level for different real-time applications and how the parasitics of the crossbar will affect the fidelity and performance of the system. The proposed architecture uses a threshold-based post-synaptic neuron, which does not require any capacitor, unlike the LIF neuron, and occupies a smaller area. A neuron refractory controller is designed to make the training process efficient by keeping track of the neuron already fired and preventing it from firing in the consecutive training phase. The CMOS memristive synapse uses an average of 0.32 nJ energy to recognize each pattern, much less than earlier works. The proposed architecture is validated using 180 nm CMOS technology.

Device-circuit co-design of memristor-based on niobium oxide for large-scale crossbar memory

Memristor-based crossbar architecture emerges as a promising candidate for 3-D memory and neuromorphic computing. However, the sneak current through the unselected cells becomes a fundamental roadblock to their development, resulting in misreading and high power consumption. In this regard, we theoretically investigate the Pt/Ti/NbO2/Nb2O5−x/Pt-based self-selective memristor, which combines the inherent nonlinearity of the NbO2 switching layer and the non-volatile operation of the Nb2O5−x memory layer in a single device. The results show that the Pt/Ti/NbO2/Nb2O5−x/Pt-based self-selective memristor offers the sneak current of 310 nA, selectivity of around 174, and on/off current ratio of 75, compared to the sneak current of approximately 70 μA, selectivity of about 4.02, and on/off current ratio of around 1.55 for the Pt/Ti/Nb2O5−x/Pt-based memristor device. Our self-selective memristor minimizes the sneak current, but a small on/off current ratio limits their readout margin and power efficiency for crossbar array size greater than 4KB. Further, we demonstrate that breaking down a large-scale crossbar array into smaller subarrays and separating them by transistor switches, called the split crossbar array, is a more efficient way of achieving a practical size crossbar array with improved readout margin and power efficiency. Our results shed light on the potential of the Pt/Ti/NbO2/Nb2O5−x/Pt-based self-selective memristor and explore the split crossbar array architecture as a practical solution to augment readout margins and power efficiency in a large-scale crossbar array.

Photoinduced Nonvolatile Resistive Switching Behavior in Oxygen-Doped MoS2 for a Neuromorphic Vision System.

Controlling resistance by external fields provides fascinating opportunities for the development of novel devices and circuits, such as temperature-field-induced superconductors, magnetic-field-triggered giant magnetoresistance devices, and electric-field-operated flash memories. In this work, we demonstrate a light-triggered nonvolatile resistive switching behavior in oxygen-doped MoS2. The two-terminal devices exhibit stable light-modulated resistive switching characteristics and optically tunable synaptic properties with an on/off ratio of up to 104. The integrated device with crossbar architecture enables simultaneous image sensing, preprocessing, and storage in a single device, thereby increasing the training efficiency and recognition rate of image recognition tasks. This work presents a novel pathway to develop the next generation of light-controlled memory and artificial vision systems for neuromorphic computing.

Effect of memristor’s potentiation-depression curves peculiarities in the convergence of physical perceptrons

Neuromorphic computing aims to emulate the architecture and information processing mechanisms of the mammalian brain. This includes the implementation by hardware of neural networks. Oxide-based memristor arrays with cross-bar architecture appear as a possible physical implementation of neural networks. In this paper, we obtain experimental potentiation-depression (P-D) curves on different manganite-based memristive systems and simulate the learning process of perceptrons for character recognition. We analyze how the specific characteristics of the P-D curves affect the convergence time -characterized by the EPOCHs-to-convergence (ETC) parameter- of the network. Our work shows that ETC is reduced for systems displaying P-D curves with relatively low granularity and non-linear and asymmetric response. In addition, we also show that noise injection during the synaptic weight actualization further reduces the ETC. The results obtained here are expected to contribute to the optimization of hardware neural networks based on memristors cross-bar arrays.

The impact of oxygen vacancy defect density on the nonlinearity and short-term plasticity of TiO2-based exponential selector

The readout margin of the one selector-one RRAM crossbar array architecture is strongly dependent on the nonlinearity of the selector device. In this work, we demonstrated that the nonlinearity of Pt/TiO2/Pt exponential selectors increases with decreasing oxygen vacancy defect density. The defect density is controlled by modulating the sputtering pressure in the oxide deposition process. Our results reveal that the dominant conduction mechanisms of the Pt/TiO2/Pt structure transit from Schottky emission to Poole–Frenkel emission with the increase of sputtering pressure. Such transition is attributed to the rise of oxygen vacancy concentration. In addition, the short-term plasticity feature of the Pt/TiO2/Pt selector is shown to be enhanced with a lower defect density. These results suggest that low defect density is necessary for improved exponential selector performances.

Strong Piezoelectricity and Improved Rectifier Properties in Mono‐ and Multilayered CuInP2S6

AbstractMost atomically thin piezoelectrics suffer from weak piezoelectric response or current rectification along the thickness direction, which largely hinders their applications in a vertical crossbar architecture. Therefore, exploring new types of ultrathin materials with strong longitudinal piezoelectric coefficient and rectification is highly desired. In this study, the monolayer of van der Waals CuInP2S6 (CIPS) is successfully exfoliated and its strong piezoelectricity in the out‐of‐plane direction with an effective coefficient d33eff of ≈5.12 pm V−1, which is one or two orders of magnitude higher than that of most existing monolayer materials with intrinsic d33, is confirmed. A prototype vertical device is further constructed and the current rectification is achieved through the flexoelectricity induced by the scanning tip force. The switching between low and high rectification states can be readily controlled by tuning the mechanical loads. These findings manifest that CIPS possesses promising application in vertical nanoscale piezoelectric devices and provides a novel strategy for achieving a good current rectification in ultrathin piezoelectrics.

BETTER: Bayesian-Based Training and Lightweight Transfer Architecture for Reliable and High-Speed Memristor Neural Network Deployment

Deep learning models implemented using memristors show high scalability and high energy efficiency, promising a compact and efficient computing architecture for resourceconstrained edge computing applications. These technologies integrate both data storage and computation simultaneously in a highly parallel memristor crossbar array architecture. However, the significant variations arising from the inherent physical randomness of memristors lead to a large performance degradation of deep learning models. The challenges of extensive energy costs and transfer time for deployment to maintain performance are faced. In this paper, for the first time, we propose a unified architecture that consists of a Bayesian-based training method and a lightweight transfer scheme. The proposed architecture can tackle the robustness, energy and time consumption issues caused by memristor variations. Our experimental results show that our architecture can double the speed and energy efficiency of deploying deep learning models.

Polymer Memristive Layer with Reduced Graphene Oxide and Al Electrodes for Tunable Memory Windows with Low-Power Operation and Enhanced Electrical Readout

Tuning memory windows is vital for cross-bar memory architectures with low power and free cross-talk. Herein, we demonstrate a synergistic interface/electrode nanoengineering strategy to tune memory windows for low power operation and enhanced electrical readout in polymer devices; this approach is workable for most insulating or semiconducting polymeric mediums. Through customizing the resistivity of selectively reduced graphene oxide nanoelectrodes, an inherent sub μA current is recorded in the programming storage state. The nanocavity of the polymer interface can reduce the switching voltage due to local electric field enhancement, thus leading to tunable memory windows. By stacking a selector onto the memory, the vertical architecture features dynamic memory kinetics, enabling cross-talk-free readout by suppressing sneak leakage current paths.

Strain investigation of PECVD passivation layer for ferroelectric domain wall random access memory

Ferroelectric domain-wall random access memory (DWRAM), based on the utilization of highly conductive domain walls in insulating ferroelectric LiNbO3 (LNO) single-crystal thin films, holds great promise for the future of memory storage. The ability to scale this technology up in a crossbar architecture means that it has the otential to surpass the storage density capabilities of commercial ferroelectric random access memory devices. Nevertheless, the passivation layer in the vertically integrated structure (VIS) architecture is critical because it affects many vital parameters of the memory such as retention, on/off current ratio, reliability, etc. Therefore, a detailed strain investigation of silicon nitride and silicon dioxide fabricated by plasma-enhanced chemical vapor deposition (PECVD) is presented. Furthermore, the effect of residual strain on the electrical properties of LNO DW cells was investigated. The results indicated that a monolayer of SiO2 or Si3N4 is not a good choice for the insulating layer because of the undesirable passivation caused by defects and residual strain. Hence, a Si3N4/SiO2 composite passivation layer is proposed, which not only solves the residual strain problem but also ensures good insulation performance. Finally, a crossbar array of DW memory cells with an on/off current ratio greater than 104 was fabricated using the Si3N4/SiO2 composite dielectric layer, demonstrating good uniformity and retention. This work validates the feasibility of high-density integration of LNO domain wall memories and provides a foundation for selecting passivation layers in the VIS architecture.

Investigating Series and Parallel Oxide Memtransistors for Tunable Weight Update Properties

Currently, analog in-memory computing, employing memristors into a crossbar array architecture (CAA), is the leading system among available neuromorphic hardware. This study presents a highly tunable synaptic weight update based on a multiterminal memtransistor device as a solution for nonlinear synaptic operations and crosstalk issues in CAA memristors, which are long-standing challenges in neuromorphic hardware applications. To explore an effective device structure for tunable weight update properties, a memtransistor device with a series and parallel structure functioning by interface type and oxygen migration is fabricated using a ZnO channel layer and an amorphous TiO2 memristor. The series memtransistor device exhibits a significant tunable weight update property at the gate knob; thus, it simultaneously can function as a selector (accelerating and inhibiting weight update) in the CAA and tune and ultimately improve the linearity of the potentiation and depression curves. Neuromorphic hardware based on tunable synaptic weight update functions provides advantageous features for accuracy and crosstalk issues. Using the Fashion-MNIST pattern recognition simulation, the tuned weight update properties are obtained by three different write and read condition combinations, and the results are close to ideal accuracy.

Performance analysis of DNA crossbar arrays for high-density memory storage applications

Deoxyribonucleic acid (DNA) has emerged as a promising building block for next-generation ultra-high density storage devices. Although DNA has high durability and extremely high density in nature, its potential as the basis of storage devices is currently hindered by limitations such as expensive and complex fabrication processes and time-consuming read–write operations. In this article, we propose the use of a DNA crossbar array architecture for an electrically readable read-only memory (DNA-ROM). While information can be ‘written’ error-free to a DNA-ROM array using appropriate sequence encodings its read accuracy can be affected by several factors such as array size, interconnect resistance, and Fermi energy deviations from HOMO levels of DNA strands employed in the crossbar. We study the impact of array size and interconnect resistance on the bit error rate of a DNA-ROM array through extensive Monte Carlo simulations. We have also analyzed the performance of our proposed DNA crossbar array for an image storage application, as a function of array size and interconnect resistance. While we expect that future advances in bioengineering and materials science will address some of the fabrication challenges associated with DNA crossbar arrays, we believe that the comprehensive body of results we present in this paper establishes the technical viability of DNA crossbar arrays as low power, high-density storage devices. Finally, our analysis of array performance vis-à-vis interconnect resistance should provide valuable insights into aspects of the fabrication process such as proper choice of interconnects necessary for ensuring high read accuracies.

A Coherent Photonic Crossbar for Scalable Universal Linear Optics

We demonstrate a novel interferometric coherent photonic crossbar architecture (Xbar) that can realize any tensor operator and allows for total loss-induced fidelity restoration, offering at the same time significant dimension scalability credentials compared to respective state-of-the-art solutions. The proposed Xbar layout demarcates from the prevalent photonic schemes that rely on the implementation of intended matrices factorized via the Singular Value Decomposition (SVD); instead, it harnesses the power of interference within a novel design where each matrix element can be mapped by one-to-one correspondence to a single, designated Xbar node, bringing down the number of programming steps to only one. In this paper, we present the theoretical foundations of the Xbar, proving that its insertion losses do not scale with the node losses as opposed to the exponential scaling witnessed by the SVD based counterparts. This leads to a matrix design with significantly lower overall insertion losses and improved scalability potential compared to SVD-based schemes, allowing for the employment of alternative node technologies with lower energy consumption and higher operational speed credentials. Finally, we theoretically validate that the proposed Xbar architecture is the first linear operator that supports fidelity restoration, outperforming SVD schemes in loss- and phase-error fidelity performance.

Ultra-low-loss multi-layer 8 × 8 microring optical switch

Microring-based optical switches are promising for wavelength-selective switching with the merits of compact size and low power consumption. However, the large insertion loss, the high fabrication, and the temperature sensitivity hinder the scalability of silicon microring optical switch fabrics. In this paper, we utilize a three-dimensional (3D) microring-based optical switch element (SE) on a multi-layer Si3N4-on-SOI platform to realize high-performance large-scale optical switch fabrics. The 3D microring-based SE consists of a Si/Si3N4 waveguide overpass crossing in the bottom and the top layers, and Si3N4 dual-coupled microring resonators (MRRs) in the middle layer. The switch is calibration-free and has low insertion loss. With the 3D microring-based SEs, we implement an 8×8 crossbar optical switch fabric. As the resonance wavelengths of all SEs are well aligned, only one SE needs to be turned on in each routing path, which greatly reduces the complexity of the switch control. The optical transmission spectra show a box-like shape, with a passband width of ∼69 GHz and an average on-state loss of ∼0.37 dB. The chip has a record-low on-chip insertion loss of 0.52–2.66 dB. We also implement a non-duplicate polarization-diversity optical switch by using the bidirectional transmission characteristics of the crossbar architecture, which is highly favorable for practical applications. 100 Gb/s dual-polarization quadrature-phase-shift-keying (DP-QPSK) signal is transmitted through the switch without significant degradation. To the best of our knowledge, this is the first time that 3D MRRs have been used to build highly scalable polarization-diversity optical switch fabrics.

BNN An Ideal Architecture for Acceleration With Resistive in Memory Computation

Binary Neural Networks (BNN) have binarized (-1 and 1) weights and feature maps. Achieving smaller model sizes and computational simplicity, they are well suited for edge-AI systems with power and hardware constraints. Recently, memristive crossbar arrays have gained considerable attention from researchers to perform analog in-memory vector-matrix multiplications in machine learning accelerators, with low power and constant computational time. Crossbar arrays suffer from many non-ideal characteristics such as memristor device imperfections, weight noise, device drift, input/output noises, and DAC/ADC overhead. Thus, for analog AI acceleration to become viable, model architectures must be robust against these non-idealities. We propose that BNN's with their binarized weights, which are ideally mapped to fewer memristive devices with less electrical characteristic issues and higher tolerance to computational noise, are a promising architecture for analog computation. In this work, we examine the viability of deploying state of the art BNNs, with features such as real value residual connections and parametric activations with biases, to analog in-memory computational accelerators. Our simulations show that BNNs are significantly more robust to crossbar non-idealities than full-precision networks, require less chip area, and consume less power on memristive crossbar architectures.

Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective.

Deep learning hasbecome ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute-in-memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute-unit to memory, known as the von Neumann bottleneck. At its heart is a cross-bar architecture with nodal non-volatile-memory elements that performs an analog multiply-and-accumulate operation, enabling the matrix-vector-multiplications repeatedly used in all neural network workloads. The memory materials can significantly influence final system-level characteristics and chip performance, including speed, power, and classification accuracy. With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material properties and the associated design constraints and demands to application, architecture, and performance. Both digital and analog memory are considered, assessing the status for training and inference, and providing metrics for the collective set of properties non-volatile memory materials will need to demonstrate for a successful CIM technology.

Nonvolatile Ferroelectric LiNbO3 Domain Wall Crossbar Memory

High-density domain wall memory based on crossbar architecture is a strong contender among next-generation high performance versatile memories due to its ultra-fast operation speed and excellent size scalability. Herein, we report 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 4 domain wall crossbar memory arrays fabricated on a LiNbO3 single crystal. Reversible creation and erasure of conducting domain walls between two antiparallel/parallel domains at bipolar write voltages enable the storage of digital “0” and “1” information. At the crosspoint of each word and bit lines, the memory cell can be accurately accessed, programmed and erased. The diode-like rectification of readout currents exhibited by all memory cells can inhibit read and write crosstalk. The electrical testing results in the crossbar memory array demonstrated the good stability of on/off currents and good uniformity of operating voltages, which can be reflected by the fact that the distribution of the coercive voltages is within 2.9 V and the “on”/ “off” current ratio is around 100 at a reading voltage of 3 V. Good data retention and fatigue resistance are also exhibited, making it possible to integrate domain wall random access memories in high density and reliability.

Quantization Design for Resistive Memories With Multiple Reads

Due to the crossbar array architecture, the sneakpath problem severely degrades the data integrity in the resistive random access memory (ReRAM). In this letter, we investigate the channel quantizer design for ReRAM arrays with multiple reads, which is a typical technique to improve the data recovery performance of data storage systems. Starting with a quantized channel model of ReRAM with multiple reads, we first derive a general approach for designing the channel quantizer, for both single-bit and multiple-bit quantizations. We then focus on the single-bit quantization, which is highly suitable for practical applications of ReRAM. In particular, we propose a semi-analytical approach to design the multiple-read single-bit quantizer with less complexity. We also derive the theoretical bit-error probability of the optimal single-bit detector/quantization as the benchmark. Results indicate that the multiple-read operation is effective in improving the error rate performance of ReRAM. Moreover, our proposed multiple-read detector outperforms the prior art detector and achieves the performance of the optimal detector.

Laser printed microelectronics

Printed organic and inorganic electronics continue to be of large interest for sensors, bioelectronics, and security applications. Many printing techniques have been investigated, albeit often with typical minimum feature sizes in the tens of micrometer range and requiring post-processing procedures at elevated temperatures to enhance the performance of functional materials. Herein, we introduce laser printing with three different inks, for the semiconductor ZnO and the metals Pt and Ag, as a facile process for fabricating printed functional electronic devices with minimum feature sizes below 1 µm. The ZnO printing is based on laser-induced hydrothermal synthesis. Importantly, no sintering of any sort needs to be performed after laser printing for any of the three materials. To demonstrate the versatility of our approach, we show functional diodes, memristors, and a physically unclonable function based on a 6 × 6 memristor crossbar architecture. In addition, we realize functional transistors by combining laser printing and inkjet printing.

Amorphous ITZO-Based Selector Device for Memristor Crossbar Array

In the era of digital transformation, a memristor and memristive circuit can provide an advanced computer architecture that efficiently processes a vast quantity of data. With the unique characteristic of memristor, a memristive crossbar array has been utilized for realization of nonvolatile memory, logic-in-memory circuit, and neuromorphic system. However, the crossbar array architecture suffers from leakage of current, known as the sneak current, which causes a cross-talk interference problem between adjacent memristor devices, leading to an unavoidable operational error and high power consumption. Here, we present an amorphous In-Sn-Zn-O (a-ITZO) oxide semiconductor-based selector device to address the sneak current issue. The a-ITZO-selector device is realized with the back-to-back Schottky diode with nonlinear current-voltage (I-V) characteristics. Its nonlinearity is dependent on the oxygen plasma treatment process which can suppress the surface electron accumulation layer arising on the a-ITZO surface. The a-ITZO-selector device shows reliable characteristics against electrical stress and high temperature. In addition, the selector device allows for a stable read margin over 1 Mbit of memristor crossbar array. The findings may offer a feasible solution for the development of a high-density memristor crossbar array.