Abstract

The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a back-end problem. The physical substructure that transfers data on the chip and ensures the quality of service begins to collapse when the size of semiconductor transistor dimensions shrinks and growing numbers of intellectual property (IP) blocks working together are integrated into a chip. The system on chip (SoC) architecture of today is so complex that not utilizing the crossbar and traditional hierarchical bus architecture. NoC connectivity reduces the amount of hardware required for routing and functions, allowing SoCs with NoC interconnect fabrics to operate at higher frequencies. Ring (Octagons) is a direct NoC that is specifically used to solve the scalability problem by expanding each node in the shape of an octagon. This paper discusses the ring NoC design concept and its simulation in Xilinx ISE 14.7, as well as the communication of functional nodes. For the field-programmable gate array (FPGA) synthesis, the performance of NoC is evaluated in terms of hardware and timing parameters. The design allows 64 to 256 node communication in a single chip with ‘N’ bit data transfer in the ring NoC. The performance of the NoC is evaluated with variable nodes from 2 to 256 in Digilent manufactured Virtex-5 FPGA hardware.

Highlights

  • Integrated circuits design and their manufacturing completely depend on the integration of different sub-modules, which are the pre-design block of the intellectual property (IP) and cores [1] at the single chip

  • The hardware chip design and synthesis were carried on Virtex-5 field-programmable gate array (FPGA), and data communication among all nodes was verified for the same topological NoC

  • The nodes are numbered as node-0 (00000000) to node-255 (11111111)

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Summary

Introduction

Integrated circuits design and their manufacturing completely depend on the integration of different sub-modules, which are the pre-design block of the IP and cores [1] at the single chip. Manufacturing and semiconductors companies are working on the new challenges in the field of networks chip design and their throughput. The systems, which generally use bus-based communication [4], are not able to meet the requirement of bandwidth, power consumption, and latency. NoC [5] is the solution for such a communicationbased system, which is a bottleneck for an embedded switching network to interconnect the different IP modules in SoCs. In comparison to the bus-based communication system, the bandwidth and design space is larger to maintain the arbitration mechanism and routing algorithms and their implementation strategies with different communication infrastructure. The current semiconductor and computer networking companies are looking the fast and reliable design and solutions in the field of computer nodes communication and technology using the single chip.

Related Work
Ring NoC
Results & Discussion
Conclusions
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