Analysis of Parasitic Effects in a Crossbar in CMOS Based Neuromorphic System for Pattern Recognition Using Memristive Synapses

Abstract

This paper proposes a complete CMOS realized neuromorphic system for pattern recognition having CMOS-based memristor emulators as synaptic circuits. The crossbar array of the system is modeled by considering the emulator circuit&#x0027;s area to determine the spacing between the interconnects. The interconnect parasitics are obtained from the ANSYS Q3D extractor. Parasitics extracted are also validated using the analytical model. A crossbar array architecture modeled with the extracted parasitic components and the memristor emulator will provide an understanding of the behavior of the crossbar array and can be used to analyze the parasitic effects on various real-time applications. Our analysis shows that as the operating frequency increases, the recognition rate of the neuromorphic system is reduced by 66.67&#x0025; due to the crossbar&#x0027;s parasitics, non-idealities of the neuron, and memristor circuits. The memristor&#x0027;s state, either low or high resistance, significantly affects the system&#x0027;s performance, which is evaluated by the rise time and signal delay. The energy consumed by the CMOS-based memristor emulator synapse for recognizing each pattern is 0.44 &#x00A0;<inline-formula><tex-math notation="LaTeX">$nJ$</tex-math></inline-formula>, which is significantly lower when compared with the previous works. The circuit design and verification are done using 180-nm CMOS technology.