Conventional Complementary Metal Oxide Semiconductor Research Articles

A memristor-based nonvolatile latch circuit

Memristive devices, which exhibit a dynamical conductance state that depends on theexcitation history, can be used as nonvolatile memory elements by storing information asdifferent conductance states. We describe the implementation of a nonvolatile synchronousflip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element.Controlled testing of the circuit demonstrated successful state storage and restoration,with an error rate of 0.1%, during 1000 power loss events. These results indicatethat integration of digital logic devices and memristors could open the way fornonvolatile computation with applications in small platforms that rely on intermittentpower sources. This demonstrated feasibility of tight integration of memristorswith CMOS (complementary metal–oxide–semiconductor) circuitry challenges thetraditional memory hierarchy, in which nonvolatile memory is only available as alarge, slow, monolithic block at the bottom of the hierarchy. In contrast, thenonvolatile, memristor-based memory cell can be fast, fine-grained and small, and iscompatible with conventional CMOS electronics. This threatens to upset the traditionalmemory hierarchy, and may open up new architectural possibilities beyond it.

Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor

In this paper, a transient voltage suppressor (TVS) using a native lateral back-to-back diode structure in conventional complementary metal–oxide–semiconductor (CMOS) technology is proposed. The capacitance, direct-current (DC) current–voltage (I–V) characteristics, and transmission line pulse (TLP) I–V characteristics of this lateral back-to-back diode are investigated. An optimization guideline for the lateral device is presented. The lateral structure is also suitable for the advanced wafer-level chip-scale package (WL-CSP) technology to meet the low capacitance and small footprint requirement for high-frequency or handheld device applications. This is a simple solution for a low-capacitance and low breakdown-voltage protection device against electrostatic discharge and electrical overstress in discrete or on-chip applications.

Electrical observation of a tunable band gap in bilayer graphene nanoribbons at room temperature

We investigate the transport properties of double-gated bilayer graphene nanoribbons at room temperature. The devices were fabricated using complementary metal-oxide semiconductor (CMOS)-compatible processes. By analyzing the dependence of the resistance at the charge neutrality point as a function of the electric field applied perpendicular to the graphene surface, we show that a band gap in the density of states opens, reaching an effective value of ∼50 meV. This demonstrates the potential of bilayer graphene as channel material for a field-effect transistor in a conventional CMOS environment.

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.

Solid-state magnetometer using electrically detected magnetic resonance

A silicon-based magnetometer utilizing spin-dependent recombination to electrically detect electron spin resonance is described. Electronic tracking of the resonant frequency provides an absolute, calibration-free measure of the magnetic field. The magnetometer can potentially be implemented entirely in conventional complementary metal–oxide–semiconductor (CMOS) integrated circuit technology. Based on published results for spin-dependent recombination in semiconductor diodes, an estimate of the achievable sensitivity and power consumption of an integrated magnetometer is derived.

A Study on Very High Performance Novel Balanced Fully Depleted Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect Transistors on Si(110) Using Accumulation-Mode Device Structure for Radio-Frequency Analog Circuits

In this study, a very high performance novel balanced complementary metal–oxide–semiconductor (CMOS) has been successfully developed on the Si(110) surface by introducing the accumulation-mode (AM) device structure at the first time. The novel balanced CMOS consists of an AM n-MOSFET and an inversion-mode (IM) p-MOSFET based on the different performances of the AM n- and p-MOSFETs, and the mechanism has been revealed. The advanced characteristics of this novel balanced CMOS transistor on Si(110) surface have also been investigated for the first time. In this paper, we experimentally demonstrate the possibility of realizing a very high performance CMOS with larger current drivability in both the n- and p-MOSFETs on Si(110) than that in conventional CMOS on Si(100). Ideal inverter characteristics have been observed in this balanced CMOS on Si(110) with only half the occupancy area of the conventional CMOS on Si(100). In addition, 1/ f noise in an AM n-MOSFET on Si(110) has been investigated and an obvious suppression has been confirmed in both the linear and saturation operation regions.

Nonvolatile memory devices with high density ruthenium nanocrystals

The nonvolatile memory transistor devices with embedded ruthenium (Ru) nanocrystals (NCs) are fabricated in a compatible way with conventional complementary metal-oxide semiconductor technology. The rapid thermal annealing for the whole gate stacks is used to form Ru NCs in pre-existed SiO2 matrix. Monocrystal Ru NCs with high density (3×1012 cm−2), small size (2–3 nm), and good uniformity both in spatial distribution and morphology are elaborated. A substantial memory window of 3.5 V is obtained and explained by the charging and effects of Ru NCs. The mechanisms of work function engineering are also discussed in this paper.

Design and Modelling of Single Electron Transistor Based Reconfigurable Adder–Subtractor

Nano electronic single electron transistor is an emerging candidate for replacing the conventional Complementary metal oxide Semiconductor devices for computing systems. Single Electron Tunneling is a promising technology, which offers greater scaling potential than Metal oxide semiconductor and it consume ultra low power. This paper investigates reconfiguration of Single Electron Encoded threshold logic gate from the logic design perspective for implementing addition and subtraction operation. A thorough analysis on computational unit has been performed and its performance in terms of area, delay and power consumption has been estimated and its suitability for higher end processing also has been evaluated.

New non‐volatile logic based on spin‐MTJ

AbstractAs the minimum dimensions of complementary metal oxide semiconductor (CMOS) transistors shrink down to 90 nm and below, some physical obstacles have been observed which prevent rigidly this miniaturization. For example, high transistor leakage currents lead to an important increase of the ‘idle’ power consumption of CMOS memory arrays. Many nanodevices are therefore the subject of research and development to help CMOS technology continue to downscale by Moore's law. Among them, the magnetic tunnel junction (MTJ) is one of the most promising candidates, because its non‐volatility offers the possibility to power off the chip to greatly reduce the ‘idle’ energy dissipation of conventional CMOS circuits. Moreover, its resistance value property (several kΩ), compatible with CMOS transistor conductivity, allows its states to be sensed easily with CMOS circuits. The novel spin transfer torque (STT) writing approach, which has been recently introduced and developed, reduces significantly the switching energy and data disturbance when compared with the conventional MTJ writing approach. It makes the MTJ technology much more suitable than other nanodevices for commercial applications. In this paper, hybrid STT‐based MTJ (spin‐MTJ)/CMOS logic circuits and some design techniques are proposed based on STMicroelectronics 90 nm CMOS technology and the published Hitachi spin‐MTJ technology. A first prototype has been simulated and evaluated. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Self-Aligned Dual-Gate Single-Electron Transistors

A novel complementary metal–oxide–semiconductor (CMOS) process compatible and self-aligned fabrication method for the dual-gate single-electron transistor (DG-SET) is presented. The performance of previous versions of the DG-SET was limited by inherent parasitic elements and its fabrication process was divergent from conventional CMOS, limiting the possibility of co-integration. Through simulation, the parasitic elements are confirmed to be caused by the non-self-alignment of the control gate, side gates, and source/drain. To resolve such issues, a new type of DG-SET was fabricated using a self-aligned process. Measurement results obtained at room temperature revealed clear Coulomb oscillation peaks in the trans-conductance curve. Through parameter extraction and its comparison with previous results, this is confirmed to be the consequence of single-electron tunneling. Also, in order to confirm that the single-electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the SOI active, low temperature measurement results for devices with different parameters is compared.

Molecular electronics in silico

Assuming with Feynman that single atoms can be used as elementary memory cells, this would give a maximum density of information units of the order of 1015 cm-2 for a planar arrangement. If the chemical composition of the surface is fixed and any information change is simply associated with an electronic or conformational change between two possible states of any given surface atom, the above arrangement would result in a maximum information density of just 1 Pbit cm-2 – peta-scale integration (PSI). The manipulation of information on the atomic scale, however, requires the use of macroscopic-scale apparatuses that may, to date, be operated only at a negligible rate. Fundamental quantum mechanical considerations show instead that electrons can be configured with bit densities of the order of 1012 cm-2 (tera-scale integration, TSI); moreover, electron presence or flow can be controlled and sensed by already existing mesoscopic-scale apparatuses in giga-scale integration (GSI). Even though there is no clear method to enable the full exploitation of the performances of such devices, the TSI density is within the reach of the present technology. Rather than scaling down conventional CMOS (complementary metal–oxide–semiconductor) circuits, TSI may almost be achieved via a hybrid architecture where a silicon-based CMOS circuit controls a nanoscopic crossbar structure hosting in each cross-point a collection of functional molecules able to mimic by themselves the behaviour of a memory cell. The hybrid (silicon + molecules) route, however, poses severe problems. The following ones have been identified as the most important: (i) the setting up of an economically sustainable technology for the preparation of cross-points with density higher than 1011 cm-2; (ii) the demultiplexing of the addressing lines to allow their linkage to the CMOS circuit; (iii) the design, synthesis, and electrical characterization of the functional molecules; and (iv) the grafting via batch processing of the functional molecules to the cross-points forming the crossbar. This paper is devoted to discuss the severe challenges posed by the hybrid architecture and to present the solutions that have been found.

Fabrication of Submicron IrO2 Nanowire Array Biosensor Platform by Conventional Complementary Metal–Oxide–Semiconductor Process

To explore the most dynamic cross field of nanotechnology and life science, and to find a more practical method of fabricating nanodevices on a very large scale with advantages of low manufacturing cost, high reliability and reproducibility, we successfully fabricated a submicron IrO2 nanowire array biosensor platform by conventional complementary metal–oxide–semiconductor (CMOS) process. Single crystal IrO2 nanowire array was grown uniformly on a 6-in. wafer surface by chemical vapor deposition (CVD) method and patterned into submicron array clusters. The obtained clusters were positioned in a designed pattern similar to a multiple electrode array (MEA) format, and each was individually addressed. The fabrication method was found to be reliable, low cost and robust. The final chip showed excellent transparency, functionality and durability.

Critical dimension metrology: perspectives and future trends

Every flowchart in microand nanofabrication includes several critical dimension (CD) metrology steps to guarantee device performance. To measure pattern density in highly-controlled processes such as lithography, plasma etching, and materials deposition, engineers traditionally employ electronor photonbased techniques. Most common in semiconductor manufacture are scatterometry, an optical diffraction-based method, and scanning electron microscopy (CD-SEM), a secondary electron emission-based technology. Although both are eminently repeatable, fast, and useful in terms of cost per measurement, will they remain state-of-the-art with the advent of ever smaller nanodevices? Indeed, as dimensions and architectures move towards sub32nm node, CD metrology, both for production process monitoring and process development, must cope with challenges presented by the latest materials, the new process flowcharts like the double patterning approach for lithography, and novel architectures such as 3D-multiwires field-effect transistor (FET) devices (see Figure 1).1–3 Therefore, accuracy of measurement at the nanometer scale in all axes (x, y, and z) represents the advent of a non-negligible factor in the race to downsize device dimensions, as illustrated in Figure 2. For the conventional complementarymetal-oxide semiconductor (CMOS) device with vertical gate and channel underneath, the single most important parameter is the bottom CD value (CD1 as indicated in Figure 2a). However, for nanowire FET devices, a full set of parameters must be tightly controlled as described in Figure 2b, with in-linemetrology including alignment, thickness, critical dimensions, and length. In addition to a multiple set of morphological outputs for future nanodevices, feature edge roughness will play a key role in the quality of device performance and in the ramp-up time for pilot lines. Indeed, as illustrated in Figure 3, as we are Figure 1. Architectures (with source, gate, and drain terminals as indicated) for field-effect transistor devices are shown in (a) and (b). Scanning electron microscope (SEM) view of a multifingers trigate device is shown in (c) and a SEM cross-section view of a multi-nanowire transistor after release of the nanowires in (d).

2007 IEEE Device Research Conference: Tour de Force Multigate and Nanowire Metal Oxide Semiconductor Field-Effect Transistors and Their Application

Scaling of the conventional planar complementary metal oxide semiconductor (CMOS) faces many challenges. Top-down fabricated gate-all-around Si nanowire FinFETs, which are compatible with the CMOS processes, offer an opportunity to circumvent these limitations to boost the device scalability and performance. Beyond applications in CMOS technology, the thus fabricated Si nanowire arrays can be explored as biosensors, providing a possible route to multiplexed label-free electronic chips for molecular diagnostics.

A non-volatile-memory device on the basis of engineered anisotropies in (Ga,Mn)As

The rich anisotropic transport behaviour shown by ferromagnetic semiconductors arises from a complex interplay of their electronic density of states and magnetic response. Such behaviour promises to enable devices whose ability to manipulate information in the form of electronic spin goes well beyond the now ubiquitous spin-valve read heads of magnetoelectronics, and on a platform that is compatible with conventional complementary metal oxide semiconductor technology. Most ferromagnetic semiconductor devices so far have relied on the bulk anisotropic behaviour of their constituent layers. Recent improvements in lithographic patterning enable the fabrication of a novel class of devices in which the anisotropy of many individual elements can be independently engineered. Here we demonstrate the first such device consisting of two nanobars with mutually orthogonal easy axes linked by a constriction. It behaves as a non-volatile memory element, where information can be written by setting the relative orientation of the magnetization of the nanobars, and read by measuring the constriction resistance.

Spin-based logic in semiconductors for reconfigurable large-scale circuits

Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge. Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors, spin injection into semiconductors from ferromagnetic metals and discoveries of new physical phenomena involving electron spin. Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward-spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow. The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a 'spin computer'. As the shrinking of conventional complementary metal-oxide-semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.

Engineering the magnetic properties of Ge1−xMnx nanowires

Possible origins of room-temperature ferromagnetism in GeMn nanowires (NWs) are investigated. Arrays of Ge1−xMnx NWs and Ge∕Ge1−xMnx nanocables (NCs) (x=1%–5%) have been synthesized within the pores of anodized alumina oxide (AAO) membranes. The influence of annealing on the magnetic properties of Ge1−xMnx NWs is studied. The room-temperature ferromagnetism is preserved after the postfabrication annealing in inert atmosphere (Tann=750°C) demonstrating overall compatibility of Ge1−xMnx NWs with conventional complementary metal-oxide semiconductor technology. The role of oxygen in high-TC ferromagnetic ordering is investigated in double-phased NCs with a Ge sheath. Despite a barrier to oxygen migration from the AAO membrane, samples still display room-temperature ferromagnetism, hence, ruling out any significant role of oxygen in the explanation of the high TC in the system. The magnetic properties of the one-dimensional Ge1−xMnx nanostructures can be understood by considering interface related phenomena.

Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor

A simple and efficient strain engineering technique for integrating the tensile-stress contact etch stop layer (CESL) process to a notch gate has been reported in detail. The strain engineering technique utilizes slight process modifications to modulate the channel stress and implantation profile for the enhancement of performance without adding any extra process steps. Compared with the conventional vertical-gate complementary metal oxide semiconductor field effect transistor (CMOSFET) with an offset spacer, a device with a notch gate as a self-aligned offset spacer achieves an extra 7% NMOS ION enhancement. The enhancement comes from the larger channel stress induced by the tensile-stress CESL on the notch gate, and is confirmed by technology computer aided design (TCAD) simulation. Moreover, fewer interface defects (Dit) and parasitic capacitances were obtained for the notch-gate samples.

Realistic limits to computation. II. The technological side

The embedding of nanometer-sized functionalised crossbars into conventional CMOS (complementary metal-oxide-semiconductor) circuits is proposed as a suitable architecture for the production of nonvolatile memories with a bit density of the order of 1011 cm-2. Solutions are proposed for the major problems that are expected to be met in this further step into the tera-scale-integration era.

Integration of lead zirconium titanate thin films for high density ferroelectric random access memory

Interests are being focused on types of nonvolatile memories such as ferroelectric random access memory (FRAM), phase change random access memory, or magnetoresistance random access memory due to their distinct memory properties such as excellent write performance which conventional nonvolatile memories do not possess. Among these types of nonvolatile memories, FRAM whose cell structure and operation are almost identical to dynamic random access memory (DRAM) can ideally realize cell size and speed of DRAM. Thus FRAM is the most appropriate candidate for future universal memory where all memory functions are performed with a single chip solution. Due to the poor ferroelectric properties of downscaled ultrathin lead zirconium titanate (PZT) capacitors as well as technical issues such as hydrogen and plasma related degradation arising from embedding ferroelectric metal-insulator-metal capacitors into conventional complementary metal oxide semiconductor processes, current FRAM still falls far below its ideally attainable cell size and performance. In this paper, based upon PZT capacitor, current mass-productive one pass transistor and one storage capacitor (1T1C), capacitor over bit line (COB) cell technologies are introduced upon which cell size of 0.937μm2 at 250nm minimum feature size technology node has been realized. And then, most recent 1T1C, COB cell technologies are discussed from which cell size of 0.27μm2 at 150nm minimum feature size technology node has been realized, and finally future three dimensional capacitor technologies for the FRAM with cell size of less than 0.08μm2 beyond 100nm minimum feature size technology node are suggested.