Critical dimension metrology: perspectives and future trends

Abstract

Every flowchart in microand nanofabrication includes several critical dimension (CD) metrology steps to guarantee device performance. To measure pattern density in highly-controlled processes such as lithography, plasma etching, and materials deposition, engineers traditionally employ electronor photonbased techniques. Most common in semiconductor manufacture are scatterometry, an optical diffraction-based method, and scanning electron microscopy (CD-SEM), a secondary electron emission-based technology. Although both are eminently repeatable, fast, and useful in terms of cost per measurement, will they remain state-of-the-art with the advent of ever smaller nanodevices? Indeed, as dimensions and architectures move towards sub32nm node, CD metrology, both for production process monitoring and process development, must cope with challenges presented by the latest materials, the new process flowcharts like the double patterning approach for lithography, and novel architectures such as 3D-multiwires field-effect transistor (FET) devices (see Figure 1).1–3 Therefore, accuracy of measurement at the nanometer scale in all axes (x, y, and z) represents the advent of a non-negligible factor in the race to downsize device dimensions, as illustrated in Figure 2. For the conventional complementarymetal-oxide semiconductor (CMOS) device with vertical gate and channel underneath, the single most important parameter is the bottom CD value (CD1 as indicated in Figure 2a). However, for nanowire FET devices, a full set of parameters must be tightly controlled as described in Figure 2b, with in-linemetrology including alignment, thickness, critical dimensions, and length. In addition to a multiple set of morphological outputs for future nanodevices, feature edge roughness will play a key role in the quality of device performance and in the ramp-up time for pilot lines. Indeed, as illustrated in Figure 3, as we are Figure 1. Architectures (with source, gate, and drain terminals as indicated) for field-effect transistor devices are shown in (a) and (b). Scanning electron microscope (SEM) view of a multifingers trigate device is shown in (c) and a SEM cross-section view of a multi-nanowire transistor after release of the nanowires in (d).