Self-Aligned Dual-Gate Single-Electron Transistors

Abstract

A novel complementary metal–oxide–semiconductor (CMOS) process compatible and self-aligned fabrication method for the dual-gate single-electron transistor (DG-SET) is presented. The performance of previous versions of the DG-SET was limited by inherent parasitic elements and its fabrication process was divergent from conventional CMOS, limiting the possibility of co-integration. Through simulation, the parasitic elements are confirmed to be caused by the non-self-alignment of the control gate, side gates, and source/drain. To resolve such issues, a new type of DG-SET was fabricated using a self-aligned process. Measurement results obtained at room temperature revealed clear Coulomb oscillation peaks in the trans-conductance curve. Through parameter extraction and its comparison with previous results, this is confirmed to be the consequence of single-electron tunneling. Also, in order to confirm that the single-electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the SOI active, low temperature measurement results for devices with different parameters is compared.