Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder

Manvinder Sharma,Digvijay Pandey,Binay Kumar Pandey,Pankaj Palta

doi:10.1007/s12633-021-01221-1

Abstract

With the integration of circuits, number of gates and transistors are increasing per chip area. However with integration in every digital circuit, the energy due to switching of gate doesn’t decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. The CMOS (complementary metal oxide semiconductor) Logic family is preferred for digital circuits due to its performance and impeccable noise margins over other families. However, in CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. The aim ofthis paper is to carry out work that is focused on reducing the power dissipation in circuits, which increases with down scaling of circuits. The experimental work is carried out on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional based CMOS circuit and PFAL based CMOS circuit. In comparison with the conventional CMOS based 2:1 multiplexer circuit, the designed PFAL based CMOS 2:1 multiplexer circuit has lesser power dissipation which is measured as 80.871 picoWatts as compared to conventional CMOS circuit which has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit has 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

Highlights

For high speed performance in computingand other applications which involve processing, computing and analysis of any signal, digital CMOS circuits have been used mostly
The possibility of reusing energy drawn from the supply and reducing the energy dissipation during switching is offered by a class of circuits known as Adiabatic logic circuits
While rate of integration of transistor per chip area is increasing day by day. This leads to power dissipation and expansive heat cooling methods

Summary

INTRODUCTION

For high speed performance in computingand other applications which involve processing, computing and analysis of any signal, digital CMOS circuits have been used mostly. As the level of clock frequency and on-chip integration will continue to grow as per the demands of faster computing, the energy and power dissipation of these high performance circuits is a perilous design issue [2]. To achieve Tera Instructions per seconds (TIPS) high end microprocessor employ billions of transistor on chip at clock rates over 30 GHz, with this rate of speed power dissipation of circuit is projected to extend to thousands of watts. Such power dissipation density introduces reliability concerns like hot carrier, thermal stress and electromigration which degrade the performance of circuits. Α is expected number of 0 to 1 transitions per data cycle, f is clock frequency

PFAL MODELING DESIGN

CONCLUSION

Ethics Approval