Modeling and Analysis of Positive Feedback Adiabatic Logic CMOS-Based 2:1 Mux and Full Adder and Its Power Dissipation Consideration

Abstract

AbstractFor high-speed performance in computing and other applications which involve processing, computing, and analysis of any signal, digital CMOS circuits have been used mostly. Several pros over other families which include perfect logic levels, impeccable noise margins, better performance, and almost negligible static power dissipation CMOS logic family is preferred. As we need faster processing of signals, the demand of these circuits is high and is going to increase in near future. With integration, the number of transistors is increasing per chip area but the energy due to gate switching does not decrease with same rate. Hence power dissipation, reduction of heat is major concern in circuits. In this work, the positive feedback adiabatic logic PFAL-based design for digital circuits using CMOS is proposed and compared with the conventional circuit. The design is simulated, and with the comparison of conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit the proposed method has less power dissipation in terms of 80.871 pW while conventional CMOS circuit has 6.9090 nW with no change in behavior of the circuit. For full adder circuit conventional CMOS has 48.0452 pW while proposed PFAL-based full adder has 3.9089 pW.KeywordsAdiabaticLow power designPFAL designMultiplexerFull adderCMOS