New non‐volatile logic based on spin‐MTJ

Abstract

AbstractAs the minimum dimensions of complementary metal oxide semiconductor (CMOS) transistors shrink down to 90 nm and below, some physical obstacles have been observed which prevent rigidly this miniaturization. For example, high transistor leakage currents lead to an important increase of the ‘idle’ power consumption of CMOS memory arrays. Many nanodevices are therefore the subject of research and development to help CMOS technology continue to downscale by Moore's law. Among them, the magnetic tunnel junction (MTJ) is one of the most promising candidates, because its non‐volatility offers the possibility to power off the chip to greatly reduce the ‘idle’ energy dissipation of conventional CMOS circuits. Moreover, its resistance value property (several kΩ), compatible with CMOS transistor conductivity, allows its states to be sensed easily with CMOS circuits. The novel spin transfer torque (STT) writing approach, which has been recently introduced and developed, reduces significantly the switching energy and data disturbance when compared with the conventional MTJ writing approach. It makes the MTJ technology much more suitable than other nanodevices for commercial applications. In this paper, hybrid STT‐based MTJ (spin‐MTJ)/CMOS logic circuits and some design techniques are proposed based on STMicroelectronics 90 nm CMOS technology and the published Hitachi spin‐MTJ technology. A first prototype has been simulated and evaluated. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)