Chip Area Research Articles

Design of CNTFET-based Ternary Ring and Up–Down Counter Cells

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)’ unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits.

A Ku-Band Broadband Stacked FET Power Amplifier Using 0.15 μm GaAs pHEMT.

To meet the application requirements of broadband radar systems for broadband power amplifiers, a Ku-band broadband power amplifier (PA) microwave monolithic integrated circuit (MMIC) based on a 0.15 µm gallium arsenide (GaAs) high-electron-mobility transistor (HEMT) technology is proposed in this paper. In this design, the advantages of the stacked FET structure in the broadband PA design are illustrated by theoretical derivation. The proposed PA uses a two-stage amplifier structure and a two-way power synthesis structure to achieve high-power gain and high-power design, respectively. The fabricated power amplifier was tested under continuous wave conditions, and the test results showed a peak power of 30.8 dBm at 16 GHz. At 15 to 17.5 GHz, the output power was above 30 dBm with a PAE of more than 32%. The fractional bandwidth of the 3 dB output power was 30%. The chip area was 3.3 × 1.2 mm2 and included input and output test pads.

High performance quaternary logic designs using GNFETs

The implementations of quaternary circuit schematics are presented in this paper. The quaternary logic is a better choice over the conventional logics because it offers high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented to design quaternary schematics using graphene nanoribbon field effect transistors (GNFETs). The dimer line of graphene nanoribbon (GN) is used to control the threshold voltage of GNFETs. Four quaternary logic inverter circuits such as standard quaternary inverter (SQI), intermediate quaternary inverter (IQI), positive quaternary inverter (PQI) and negative quaternary inverter (NQI) along with the NAND and NOR circuits are proposed. Furthermore, the quaternary half adder circuit is designed that helps to develop complex designs. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). The obtained circuit performances are compared with carbon nanotube FETs (CNFETs) based circuits. The comparison results show that the proposed GNFET circuits achieved 53.51% of overall performance improvement over the CNFET circuits.

Quantum-dot light-chip micro-spectrometer.

Micro-spectrometers have great potential in various fields such as medicine, agriculture, and aerospace. In this work, a quantum-dot (QD) light-chip micro-spectrometer is proposed in which QDs emit different wavelengths of light that are combined with a spectral reconstruction (SR) algorithm. The QD array itself can play the roles of both the light source and the wavelength division structure. The spectra of samples can be obtained by using this simple light source with a detector and algorithm, and the spectral resolution reaches 9.7 nm in the wavelength range from 580 nm to 720 nm. The area of the QD light chip is 4 × 7.5 mm2, which is 20 times smaller than the halogen light sources of commercial spectrometers. It does not need a wavelength division structure and greatly reduces the volume of the spectrometer. Such a micro-spectrometer can be used for material identification: in a demonstration, three kinds of transparent samples, real and fake leaves, and real and fake blood were classified with an accuracy of 100%. These results indicate that the spectrometer based on a QD light chip has broad application prospects.

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

The quality of the silicon carbide (SiC) epitaxial layer, i.e., layer homogeneities and extended defect densities, is of highest importance for high power 4H-SiC trench metal-oxide-semiconductor field effect transistors (Trench-MOSFET) devices. Especially, yield for devices with a large chip area is severely impacted by extended defects. Previously, devices had to be fully manufactured to effectively gauge the impact of a reduction in extended defect densities in the epitaxial layers on device yield. The production of devices such as Trench-MOSFETs is an extensive procedure. Therefore, a correlation between extended defects in the epitaxial layer and electrical device failure would allow to reliably estimate the impact of process changes during epitaxial layer deposition on electrical device yield.For this reason, n-type epitaxial layers were grown on around 1,000 commercially available 150 mm 4H-SiC Si-face substrates, which received a chemical wet cleaning prior to the epitaxy deposition. Substrates with lowest micro-pipe density from two different suppliers were used. The wafers were characterized with the corresponding device layout for defects utilizing surface microscopy as well as ultraviolet photoluminescence techniques. Subsequently, these wafers were used to produce more than 500,000 Trench-MOSFET devices. All devices have been tested on wafer level for their initial electrical integrity.With these methods a precise correlation between extended defects in the epitaxial layer and electrical failures on wafer level could be found. The influence of different substrates on the defect-based yield prediction regarding the electrical yield on wafer level is discussed. Additionally, a calculated kill-ratio is presented and the severity of defect classes on initial device failure, e.g., stacking faults, and their key failures modes are discussed.

A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers

This brief proposes a low voltage ultra-low power 10-bit 100-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To overcome the performance degradation due to the signal-related current fluctuation under lower supply voltage, an adaptive-biasing comparator with current self-compensation (CSC) technique is proposed to obtain a constant working current, reducing the minimum supply voltage from 0.7V in conventional ADCs to 0.55V. Since full-scale range shrinks with the supply voltage, voltage undershoot in power rail caused by capacitor digital-to-analog converter (C-DAC) deteriorates effective-number-of-bits (ENOB). Conventional solutions involve enhanced regulators and large decoupling capacitors, which cost remarkable power dissipation and large chip area. This brief presents a pulse-injection undershoot compensation technique which reduces the DAC-related supply fluctuation from a typical 15mV to 1.8mV, and improves the ENOB by 0.4 bit. The prototype was fabricated in TSMC 28nm HPC CMOS technology. The proposed SAR ADC achieves an SNDR of 54.7dB and an SFDR of 68dB with the power consumption of 0.16mW under 0.55V supply voltage, a figure of merit (FoM) of 3.6-fJ/conversion-step is achieved. The chip area of the ADC core is 130μm×225μm.

A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing

Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in high-throughput and high-resolution cases. This paper proposes an analog-oriented RRAM array/read circuits co-design technique to solve the trade-offs between distortion, power consumption, throughput, and chip area. In previous works, the RRAM array is built in a digital mindset that access transistors only serve as switches. Instead, this work investigates a new perspective that utilizes access transistors as common-gate current buffers which reduce the operating current and amplify the output impedance. To further decrease the complexity of peripheral circuits, the idea of In-ADC Computing (IAC) is proposed, which performs shift-add operation together with analog-to-digital conversion. Benefiting from proposed ideas, a pre-trained VGG-8 network based on the CIFAR-10 dataset can be implemented and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit MAC operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still be able to operate in a power-efficient way.

The Research on the Fabrication of the Novel Basic Unit for 3D Structure Integrated Circuit

The IC industry in the Chinese mainland has encountered the difficulty caused by the embargo on lithography machines in developing state-of-the-art semiconductor IC processes. For the first time, this work fabricates out the HVTFET which we have independent intellectual property rights. A 50 nm channel length N HVTFET device is fabricated successfully using a 0.35 µm process, and its characteristics are close to those of TSMC’s 55 nm planar N MOSFET. The experimental results of this paper have two important significances. First, it shows that the fabrication of the advanced ICs in the Chinese mainland can get rid of the limitation of the lithography machine by using the HVTFET. Second, it shows that it is possible to decrease the chip area by about 3/4 by using the HVTFET structure for the ICs with 28 nm and above planar MOS processes, which are quite common in China.

Design of a multi-modulus divider with a wide frequency dividing range and low power consumption

A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.

Design and VLSI implementation of SRAM memory array using Application-specific Integrated circuits design flow

Abstract Static Random-access memory (SRAM) are useful structure blocks in operations like data storage, embedded operations, cache recollections, microprocessors. The circuits should retain larger impunity to noise voltages. So, the Stationary Noise Margin (SNM) of the circuits should be veritably high. Large SRAM arrays that are extensively used as cache memory in microprocessors and operation-specific integrated circuits can absorb a big portion of the chip area. Highly compact circuits like SRAM arrays are estimated to cover relatively 90% of the System on chip area within the coming years. To optimize the performance of similar chips, large arrays of fast SRAM help to speed up the system performance. As a result, numerous minimal-size SRAM cells are tightly packed making SRAM arrays the compact circuitry on a chip. In this work an attempt is made to design a 8 X 8 SRAM memory array along with different components like Write driver circuit, Pre-charge circuit, Row and Column Decoder. Different SRAM architectures such as 6T, 7T and 8T are designed and different parameters such as Static Noise Margin and power dissipated are measured and the best performing memory design has been selected. 8T design has been resulted with least power dissipation. Hence this cell is selected for designing the memory array. A schematic of 8 x 8 array is designed and the layout of single SRAM 8T is created and to complete the ASIC design flow, DRC is done and the pre and post simulation are compared and verified. The integrated SRAM is operated with an input voltage of 0 to 1.8V.

A reconfigurable dual‐band low noise amplifier for 5G in 65‐nm CMOS

AbstractIn this paper, a reconfigurable low noise amplifier (LNA) is proposed for 5G dual‐bands in a 65‐nm CMOS process. The reconfigurable function of LNA is realized by designing reconfigurable matching networks composed of transformers and MOS transistor switches. The pole characteristics of the resonant network composed of the reconfigurable network and the equivalent circuit of the amplifying device are deduced and analyzed in detail. By establishing the relationship between two reconfigurable frequencies and the ratio of transformer coil inductance under two switching states, the position of the switch and the specific parameters of the reconfigurable matching network are determined. Measurement results show small‐signal gain of 25.5 to 33.9 dB and noise figure of 3.3 to 4.3 dB at 24 to 29.5 GHz bands, and small‐signal gain of 23.5 to 27.8 dB and noise figure of 4.3 to 4.5 dB at 37 to 40 GHz bands, respectively. The chip area occupied 0.34 mm2 including pads.

The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals

An adaptive filter is the utmost essential filter castoff in statistical signal dealing. The fine-tuning of the filter factor in relation to the response signal is the adaptive filter's key feature due to fewer calculations, Least Mean Square (LMS) adaptive filters are widely used to remove noise from Electrocardiograms (ECG). The adaptive filters are realized as signal processing algorithms in Digital Signal Processors (DSPs) or in VLSI Signal Processors (VSPs). The technique provides a way to create a folded adaptive lattice LMS filter, which requires less hardware than an adaptive lattice filter. Folding is an algorithm that uses a time scheduling technique that combines arithmetic operations into one operation which reduces Register and silicon chip areas. The design and implementation of a folded lattice adaptive filter remove Power Line Interference (PLI) noise from ECG signals. The MATLAB Xilinx System Generator tool is used to design the Adaptive Lattice LMS Filter and Folded Adaptive Lattice LMS Filter with Folding Order K = 2 and K = 4 and realized in the Virtex 5 FPGA KIT. The results of the folded architecture show that the area is reduced for K = 2 and K = 4 by 82.60% and 91.05%, respectively compared with a normal adaptive lattice filter.

Design and Implementation of Low Power Time-To-Digital Converter using MGDI Technique

This paper introduces a novel Time to Digital Converter (TDC) architecture based on the Modified Gate Diffusion Input (MGDI) technique, which is derived from the well-established GDI method. Through the utilization of MGDI-based logic gates and digital circuitry, this innovative approach leads to a substantial reduction in the number of transistors required for implementation. As a result, it offers significant advantages in terms of circuit area, power consumption, and propagation delay, while simultaneously simplifying the complexity of the overall logic design. The functional blocks within the TDC have been optimized to efficiently process an internal clock frequency of 5MHz. This achievement is realized using cutting-edge 90nm MGDI technology, operating at a supply voltage of 1V. Practical implementation of this design can be carried out seamlessly with Cadence Virtuoso tools in the 90nm technology node. In essence, this research effort represents a promising advancement in the realm of time-to-digital conversion. By harnessing the capabilities of MGDI and its transistor-saving attributes, the proposed TDC not only enhances performance but also addresses critical concerns such as power efficiency and chip area utilization. These advancements make it a compelling choice for applications requiring precise time measurements, while the compatibility with contemporary technology nodes ensures its relevance and applicability in modern integrated circuit design.

Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications

This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.

Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor

Aggressive voltage scaling to reduce energy consumption in Multicore causes exponential cell failures in SRAM. Last-level-cache (LLC), the major contender of chip area, exhibits highest sensitivity to low voltage parametric failures and limits energy efficiency. To break the energy barrier, exclusive fault protection mechanism is solicited to ensure on-chip data recovery out of the low voltage failures. This work proposes Cache evolution for energy efficiency by protecting cache blocks from SRAM cell failures due to voltage scaling. A set of coherence and reuse aware in-cache selective replication policies are proposed to ensure on-chip data recovery. Reuse likelihood is predicted through a vector optimization technique using Genetic Algorithm (GA). Reuse aware selective invalidation is employed to balance cache load due to replications. A replication aware replacement policy is also developed that victimizes the lowest reusable cache block. The proposed scheme is evaluated in Multi2Sim 5.0 simulation framework with SPEC CPU benchmark programs. Experimental results claim 43.66% and 38.80% reductions in miss rate and 59.10% and 52.73% reductions in vulnerability for integer and floating point benchmarks respectively. Energy reduction of 39.21% is observed for integer and 25.73% is observed for floating point benchmarks. Up to 34.78% and 26.98% power reductions in integer and floating point benchmarks are also observed. The minimum supply voltage of 350 mV is achieved at the cost of 7.05% area overhead and 3% performance drop-off.

Design of a GaAs-Based Ka-Band Low Noise Amplifier MMIC with Gain Flatness Enhancement

This paper presents a GaAs-based Ka-band low noise amplifier (LNA) with gain flatness enhancement. Active device optimization and inductive degeneration techniques were employed to obtain a low noise figure (NF) and good input/output return loss. In order to achieve a flat gain response over a wide bandwidth, the stagger tuning technique was utilized. The proposed LNA was implemented by 0.15 μm GaAs pHEMT process, and the chip area is only 1.5 × 0.9 mm2. Measurement results show that the presented LNA exhibits a small signal gain of 21.5 ± 0.3 dB, and the NF of the LNA is less than 2.2 dB from 32 to 40 GHz at room temperature.

A level shifter for high-side GaN drivers with enhanced dV/dt immunity and speed

—In this paper, a level shifter with high dV/dt immunity and high speed is presented for GaN drivers. During dV/dt transitions of floating power supply, a resistor-based decoupling technique (RDT) is applied for the level shifter to completely eliminates the interference of dV/dt-induced noise on the output logic. A cross-controlled noise blanker (CCNB) is also added to further improve the reliability of output logic. The dV/dt immunity of the level shifter is significantly improved. Moreover, a short pulse charging circuit helps speed up response speed during level shifting. This circuit has been fabricated in a 0.35 μm 100 V HV CMOS process and occupies an active chip area of 0.055 mm2. Experimental results confirm that the proposed level shifter works at 5 MHz, achieving 80V/ns dV/dt immunity with a small figure of merit (0.057ns/(μm⋅V)).

A chip activation protocol for preventing IC recycling

Penetration of recycled integrated circuits into electronic components’ supply chain has been a major concern in recent decades. Due to shorter lifetime compared to original counterparts, deploying recycled components into electronic products can cause potential reliability and performance issues, apart from economic loss for the chip manufacturers. Current countermeasures proposed for addressing IC recycling can only detect counterfeit components, but cannot prevent them from entering into the supply chain, yet no prevention approach has been introduced for this purpose. In this paper, a chip activation protocol is proposed which, once approved and standardized among chip manufacturers, can actively protect ICs against recycling attacks. In this approach, each integrated circuit performs a simple and lightweight authentication procedure and enters into its normal operation mode only when the authentication procedure succeeds. Recycled ICs would be non-functional due to failed authentication. Experimental results on a 32-bit microprocessor reveal that the proposed approach incurs low overhead to the chip area, while imposing zero timing overhead to the normal operation of the chip.

Electronically tunable compact inductance simulator with experimental verification

AbstractA novel inductance simulation circuit employing only two dual‐output voltage‐differencing buffered amplifiers (DO‐VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor‐less realization that provides electronically controllable realized inductance through biasing quantities of DO‐VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO‐VDBAs and does not exhibit instability at high frequencies. The simple and compact metal‐oxide semiconductor (MOS) implementation of the DO‐VDBAs (eight MOS per DO‐VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on‐chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF‐356.