Design of a multi-modulus divider with a wide frequency dividing range and low power consumption

Abstract

A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.