Chip Area Research Articles

A high current efficiency multipath nested feedforward compensation technique for two-stage amplifier

In this paper, a high current efficiency two-stage amplifier using multipath nested feedforward compensation (MNFC) method is proposed. For the purpose of achieving the high current efficiency, the first stage of the amplifier uses a recycling folded cascode amplifier (RFC) and a nested small-gain stage is added between the two stages of the amplifier so that there are two paths in the feedforward path. This two-stage amplifier improves the phase margin (PM) and extends the gain bandwidth (GBW) by using the MNFC technique which can eliminate the non-dominant pole. The chip area of this two-stage MNFC amplifier which using 0.18μm CMOS process is 0.01272 mm2. The simulated and measured results shows that the phase margin(PM), DC gain, gain-bandwidth(GBW), average 1% settling time, slew rate- (SR-) and slew rate+ (SR+) is 72.7°, 104.4 dB, 4.29 MHz, 246.2 ns, 16 V/μs, and 6.15 V/μs, respectively, when the load capacitance is 120 pF. The supply voltage of this circuit is 1.8 V and the power consumption is 0.13 mW.

A Fast Interface Circuit for the Measurement of 10 Ω to 1 GΩ Resistance

In this work, an interface circuit applied to resistive gas or chemical sensors is proposed. The interface circuit includes a detection front-end, a single-end to differential circuit, a successive approximation analog-to-digital converter (SAR ADC), and some reference auxiliary circuits. In detection front-end circuits, mirrored currents in a current mirror usually differ by several orders of magnitude. In order to ensure that the current mirror can be copied accurately, this work uses a negative feedback structure consisting of an operational amplifier and an NMOS tube to ensure that the VDS of the current mirroring tube remains consistent. Simulation results show that the replication error of the current mirror is 0.015%. The proposed interface circuit has a detection range of 10 Ω to 1 GΩ with a relative error of 0.55%. The current multiplication or divided technique allows the interface circuit to have a high sampling frequency of up to 10 kHz. The proposed circuit is based on a 180 nm CMOS process with a chip area of 0.308 mm2 (723 μm ∗ 426 μm). The power consumption of the whole interface circuit is 3.66 mW when the power supply voltage is 1.8 V.

Multi-objective Floorplanning optimization engaging dynamic programming for system on chip

The quest for optimal VLSI Floorplanning (FP) addressing noteworthy challenges namely Area, Wirelength, and Temperature remains an ongoing field of research. Prevailing FP designs individually optimize these constraints that increase the model complexity with reduced efficiency. Given this motivation, this study provides an optimum FP aimed at minimizing the overall chip area by adhering to the standard design requirements. Accordingly, the divide-and-conquer model of Dynamic Programming (DP) adopted in this work simultaneously optimizes the chip area by devising separate analytical cost functions related to the physical design parameters that are then collated to yield the compact Floor plan. The formulated DP optimization coined as Weighted Aggregated DP-Based FP (WADPFP) adaptively tunes the cost function using rank-sum scaled weights and the discount factor thereby reducing congestion and hotspots. This objective is met using two novel recursive functions ensuring temperature and area scalability. Simulation and synthesis of the proposed FP on the Microelectronic Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) Benchmark circuits demonstrated the viability of the automated FP design by registering 6.05%, 13%, and 4.35% reduction in area, wirelength, and temperature respectively in comparison with the traditional and recent peers. Additional analysis on the AMI49_X benchmark circuits emphasizes the scalable nature of the introduced WADPFP.

Analysis and Design of a Gain-Enhanced 1–20-GHz LNA With Output-Stage Transformer Feedback

A gain-enhanced technique with output-stage transformer feedback (OSTF) for the low-noise amplifiers is proposed in this brief. The transformer is realized by a pair of magnetically coupled microstrip lines between the drain and source stages, one of which acts as a series-peaking inductor and the other as a source degenerate inductor. By adjusting the length and gap of the magnetically coupled microstrip lines, the tuning of the gain in high frequency is realized. To verify the proposed OSTF gain-enhanced scheme, two LNAs with the same structure are designed, with one having OSTF and the other not. The gainenhanced wideband LNA with OSTF is fabricated in 0.15-GaAs pseudomorphic high-electron mobility transistor process. The total chip area, including input and output testing pads, is 1.24 mm2. The simulated results show excellent performance with a maximum gain improvement of 3-dB at 20 GHz. The measured results show that the gain-enhanced LNA has an average gain of 22.6 dB and a noise figure below 2 dB from 1 to 20 GHz, which are in good agreement with simulated ones.

Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA

One technique to overcome the exponential growth bottleneck is to increase the number of cores on a processor, although having too many cores might cause issues including chip overheating and communication blockage. The problem of the communication bottleneck on the chip is presently effectively resolved by networks-on-chip (NoC). A 3D stack of chips is now possible, thanks to recent developments in IC manufacturing techniques, enabling to reduce of chip area while increasing chip throughput and reducing power consumption. The automated process associated with mapping applications to form three-dimensional NoC architectures is a significant new path in 3D NoC research. This work proposes a 3D NoC partitioning approach that can identify the 3D NoC region that has to be mapped. A double particle swarm optimization (DPSO) inspired algorithmic technique, which may combine the characteristics having neighbourhood search and genetic architectures, also addresses the challenge of a particle swarm algorithm descending into local optimal solutions. Experimental evidence supports the claim that this hybrid optimization algorithm based on Double Particle Swarm Optimisation outperforms the conventional heuristic technique in terms of output rate and loss in energy. The findings demonstrate that in a network of the same size, the newly introduced router delivers the lowest loss on the longest path. Three factors, namely energy, latency or delay, and throughput, are compared between the suggested 3D mesh ONoC and its 2D version. When comparing power consumption between 3D ONoC and its electronic and 2D equivalents, which both have 512 IP cores, it may save roughly 79.9% of the energy used by the electronic counterpart and 24.3% of the energy used by the latter. The network efficiency of the 3D mesh ONoC is simulated by DPSO in a variety of configurations. The outcomes also demonstrate an increase in performance over the 2D ONoC. As a flexible communication solution, Network-On-Chips (NoCs) have been frequently employed in the development of multiprocessor system-on-chips (MPSoCs). By outsourcing their communication activities, NoCs permit on-chip Intellectual Property (IP) cores to communicate with one another and function at a better level. The important components in assigning application duties, distributing the work to the IPs, and coordinating communication among them are mapping and scheduling methods. This study aims to present an entirely advanced form of research in the area of 3D NoC mapping and scheduling applications, grouping the results according to various parameters and offering several suggestions for further research.

A ku-band common-leg transceiver with built-in configurable register in 130-nm CMOS technology for phased-array systems

To solve the bottleneck of amplitude and phase accuracy deterioration caused by process and unpredictable errors, this paper proposes a Ku-band common-leg transceiver with built-in configurable register to achieve 64-state amplitude and phase accuracy correction, respectively, by redefining control codes of each state after taping out. Two-stage cascaded variable gain amplifiers (VGAs) and the vector-summing phase shifter (VSPS) with tail current source controlled by DAC are adopted to achieve large amplitude and phase coverage of 31.5 dB with the LSB of 0.5 dB and 360° with the LSB of 5.625°, respectively. According to the measurement results, in the frequency range of 14–18 GHz, the chip has amplitude accuracy with the root mean square (rms) error of ＜ 0.4 dB, while the rms phase error is ＜ 5.3°. The phase shifting accuracy is measured to be ＜ 2.2°, while the rms amplitude error is ＜ 0.67 dB. The receiving and transmitting channels have reference gain of 3.6–6 dB and 8–10.4 dB, respectively. The whole transceiver occupies 3 × 2.3 mm2 chip area including pads.

Compact Bandwidth-Enhanced 180-Degree Phase Shifter Using Edge-Coupled Multi-Microstrip and Artificial Transmission Line.

Compactness has obtained sufficient importance in wideband phase shifter design considerations, as it is directly related to fabrication cost. In this paper, a novel structure was presented to create compact broadband 180-degree phase shifter, which has the advantages of enhanced bandwidth and significantly reduced chip area. The proposed configuration consists of edge-coupled multi-microstrip lines (ECMML) and an artificial transmission line (ATL) with dual-shorted inductors, both of which have the periodic shunt load of capacitors. The ECMML can provide a high coupling coefficient, leading to an increase in the bandwidth, while the introduced capacitors can greatly reduce the line length (35.8% of the conventional method). To verify the relevant mechanisms, a wideband switched network with compact dimensions of 0.67 × 0.46 mm2 was designed via 0.15-micrometer GaAs pHEMT technology. Combined with the measured switch transistor, it was shown that the proposed phase shifter exhibits an insertion loss of less than 2 dB, a return loss of greater than 12 dB, a maximum phase error of less than 0.6° and a channel amplitude difference of less than 0.1 dB in the range of 10 to 20 GHz.

A Fully Integrated RFID Reader SoC.

The traditional RFID reader module relies on a discrete original design. This design integrates a microcontroller, high-frequency RFID reader IC and other multiple chips onto a PCB board, leading to bottlenecks in cost, power consumption, stability and reliability. To align with the trend towards high integration, miniaturization and low power consumption in RFID reader, this paper introduces a fully integrated RFID Reader SoC. The SoC employs the open-source Cortex-M0 core to integrate the RF transceiver, analog circuits, baseband protocol processing, memory and interface circuits into one chip. It's compatible with ISO/IEC 14443 A-type and B-type and ISO/IEC 15693 transmission protocols and rates. Manufactured using a 0.18 μm process, the chip is compatible with multiple standards. The optimized design of the digital baseband control circuit results in a chip area of only 11.95 mm2 offering clear advantages in both area and integration compared to similar work.

(Keynote) Technological Challenges and Emerging Device Architectures for Future Semiconductor Micro and Nanoelectronics

Semiconductor technology has known an exponential evolution in the last decades and is fully integrated in our everyday life. According to the Semiconductor Industry association (SIA) the global semiconductor industry sales reaches about US$ 700 billion in 2023, corresponding with a shipment of more than 1.2 trillion components. This necessitates implementation of many novel materials, advanced design concepts and new transistor structures.Increased device performance and reduced power consumption, while maintaining a good manufacturability and yield performance without penalizing the cost/function, are driving microelectronic research towards 3-nm technologies. A large variety of device architectures such as FinFETs, TFETs, negative capacitance, Gate-All-Around, nanowires (NWs), nanosheets (NSs) in both horizontal or vertical configurations, CFET and Forksheet structures are extensively investigated for both logic and analog/RF building blocks enabling System-on-Chip (SoC) applications.In addition to the huge progress achieved in silicon technology, heterogenous integration of Ge and III-V technologies on a silicon platform shows a strong potential, leading towards the on-chip integration of building blocks with different functionality. The fact that both Ge and III-V materials can be selectively grown on Si has strongly triggered the interest in heterogeneous integration.Wide bandgap materials such as GaN offer unique features for RF applications used in base stations for mobile communication, complementing the performance of Si devices suffering from limited output power. These materials can epitaxially be grown on Si substrates. One of the main challenges related to the hetero epitaxy of III-V materials on a Si substrate is the control of extended defects due to the lattice mismatch of the different materials. In recent years, there has been a strong increase in the commercial availability of GaN devices, although for certain applications there is a competition with SiC.Complex and dense SoC applications can be realized by 3D wafer stacking using Through-Silicon-Vias (TSV) for wafer-to-wafer bonding. The 3D integration results in a reduction of the RC product and interconnect length, a smaller form factor and enables vertical partitioning. Main challenges are the TSV process module itself (e.g. Cu via filling, mechanical stress, contamination, keep-out-zone), the wafer thinning and handling and the 3D stacking technology (stacking density, pitch, chip-to-chip interconnect etc.). Very promising results are obtained for monolithic sequential 3D (S3D) processing based on the processing of different tiers on top of each other. Difference can be made between transistor level (n- and pMOS), CMOS level (different standard cells in different tiers) and IP block level for the partitioning. In this way it is e.g. possible to process first CMOS circuits in the Si substrate and then further processing in a III-V layer on top. Benefits are related to an enhanced device density per chip area and a shorter interconnection length. A low cost less scalable tier can be processed on top of an expensive scalable tier as done in the case of logic-memory integration.Major trends in above mentioned process integration approaches are reviewed and technological challenges of some process modules and device structures highlighted.

Bulk-driven CMOS linear transconductance-cell for AC amplifiers with very low cut-off frequency

This manuscript proposes a novel linearized transconductor for AC amplifiers with a very low cut-off frequency. The cell uses an alternative solution that is based on a modified source-degeneration OTA, using two bulk-driven buffers, incorporating bootstrapping techniques to a buffer and a degenerated resistor. In the buffer, the bootstrapping effect is implemented by using a pseudo-resistor and a linear capacitor properly configured, whereas in the resistor the output voltages of the buffers are used with this goal. Thus, the proposed solution allows realizing a very large time constant, avoiding the use of very large size resistors and capacitors, thus saving chip area. The technique is demonstrated in an 0.18μm CMOS technology by designing an OTA operating with a supply voltage of 0.6 V and achieving a low cut-off frequency of around 2Hz with a power consumption of 462 nW.

A weak current detection circuit with LDO for electrochemical sensors

Electrochemical sensors applied in single molecules detection can only trigger a weak pA-level current, which is hard to detect. In this paper, a weak current detection circuit with LDO for electrochemical sensors is presented to achieve high-precision measurement. A precision transimpedance amplifier with a novel Input bias current elimination technique is used to amplify the weak current. In addition, a stable electric potential difference to the electrodes of the sensor needs to be provided when the electrochemical sensors operate, so a novel low-power LDO was designed, which provides a 3.3 V stable voltage. The chip has been manufactured in a 0.35 μm BCD process and occupies an active chip area of 1.83 mm*2.10 mm. Experimental results confirm that the proposed TIA has an input bias current of maximum 93 fA. The circuit can detect the current signal from 2 pA to 7 nA. The input integrated noise current of the detection circuit is 0.23pArms. The LDO of the chip supplies an output voltage of 3.3 V and consumes 50 nA of quiescent current.

Vertical Multi-Junction Laser Power Converters with 61% Efficiency at 30 W Output Power and with Tolerance to Beam Non-Uniformity, Partial Illumination, and Beam Displacement

Stable and reliable optical power converting devices are obtained using vertical multi-junction laser power converters. They are based on the GaAs and the InP material systems and are used for power-over-fiber or power-beaming applications. This study demonstrates that, in addition to providing the overall best conversion efficiencies with output voltages ideal for various applications, these semiconductor photovoltaic devices are very tolerant to beam non-uniformity, partial illumination, or beam displacement variations. Examples are given with two tight beams, each covering as little as ~7% of the cell area. An optical input power of 10 W was converted with still an efficiency of Eff ~59.4%. For an input power of 20 W, the illuminated area was set to ~22% without significantly affecting the conversion efficiency of Eff ~60%. Remarkably, for a beam diameter at ~65% of the chip length (i.e., covering ~35% of the chip area), a converted power of 29.5 W was obtained using a 12-junction GaAs device with a conversion efficiency of 61%. For a 10 junction InP-based device, an efficiency of Eff = 51.1% was obtained at an output voltage reaching as high as Voc = 5.954 V for an average optical intensity of 69 W/cm2 and an illumination area of ~57%.

A 2.4 GHz low-power and compact 3-bit active phase shifter utilizing miller capacitance

A low-power and compact 3-bit active phase shifter is designed and implemented in a 22 nm FDSOI CMOS process. A modified inverter-based topology, which takes advantage of miller capacitance, is used to create a compact and low-power solution, resulting in ∼10× and ∼90× reduction in the power and chip area, respectively, for a given phase shift, compared to the standard inverter-based topology. At the same time, the proposed phase shifter exhibits less sensitivity to device mismatch. The proposed design measures ∼0.004 mm2, consumes 1.8 mW, and delivers up to 65°of phase shift with RMS phase and amplitude error of 3.85°and ±0.34 dB, respectively. The measured die-to-die variation is also confined to ±6.2°, which is <10% of the full range.

Dynamic fragmentation and chip formation of water-soaked rock in linear cutting with a coupled moisture migration-fracture model

Water can greatly influence the mechanical properties and dynamic fracture of underground rock mass. However, the dynamic fragmentation and chip formation of water-soaked rock in linear cutting is neglected. In this work, a coupled moisture migration-fracture model is utilized to investigate this problem. First, the water weakening effect on rock mechanical parameters is introduced in the coupled model according to a fitting laboratory test. Then, the uniaxial tensile, uniaxial compression, triaxial compression, and swelling experiments are utilized to calibrate the input micro-parameters. Subsequently, a series of scratch tests are carried out on the water-soaked rock samples. The stress evolution, fragmentation mode, cutting force, crack number, extent of fracture zone, chip shape, chip area, cutting work, and mechanical specific energy (MSE) with different water content are studied. The results indicate that as water content increases, the rock sample changes from brittle failure to ductile failure in linear cutting, the peak cutting force gradually decreases, and the chip area first becomes larger and then smaller, while the MSE shows an opposite trend. Especially, a water content of 2% can bring the largest chip area and the highest cutting efficiency. Moreover, the effects of cutting velocity and cutting depth on the above indexes are discussed. Finally, a complex specimen composed of half wet and half dry rock is built to further demonstrate the influence of water on rock dynamic fragmentation and chip formation in linear cutting. The modeling results in this paper provide new insights into the influence mechanism of water on rock dynamic fragmentation, chip formation, and cutting efficiency in linear cutting.

Structural Optimization Design of Microfluidic Chips Based on Fast Sequence Pair Algorithm.

The market for microfluidic chips is experiencing significant growth; however, their development is hindered by a complex design process and low efficiency. Enhancing microfluidic chips' design quality and efficiency has emerged as an integral approach to foster their advancement. Currently, the existing structural design schemes lack careful consideration regarding the impact of chip area, microchannel length, and the number of intersections on chip design. This inadequacy leads to redundant chip structures resulting from the separation of layout and wiring design. This study proposes a structural optimization method for microfluidic chips to address these issues utilizing a simulated annealing algorithm. The simulated annealing algorithm generates an initial solution in advance using the fast sequence pair algorithm. Subsequently, an improved simulated annealing algorithm is employed to obtain the optimal solution for the device layout. During the wiring stage, an advanced wiring method is used to designate the high wiring area, thereby increasing the success rate of microfluidic chip wiring. Furthermore, the connection between layout and routing is reinforced through an improved layout adjustment method, which reduces the length of microchannels and the number of intersections. Finally, the effectiveness of the structural optimization approach is validated through six sets of test cases, successfully achieving the objective of enhancing the design quality of microfluidic chips.

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.

MF-RALU: design of an efficient multi-functional reversible arithmetic and logic unit for processor design on the field programmable gate array platform

Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The MF-RALU utilizes a &amp;lt;11% chip area and consumes 332 mW total power. The RISC processor utilizes a &amp;lt;3% chip area and works at 483 MHZ frequency by consuming 159 mW of total power on Artix-7 FPGA.

An efficient ultra-wideband digital transceiver for wireless applications on the field-programmable gate array platform

&lt;p&gt;The ultra-wideband (UWB) technology is a promising short-range communication technology for most wireless applications. The UWB works at higher frequencies and is affected by interferences with the same frequency standards. This manuscript has designed an efficient and low-cost implementation of IEEE 802.15.4a-based UWB-digital transceiver (DTR). The design module contains UWB transmitter (TX), channel, and UWB-receiver (RX) units. Convolutional encoding and modulation units like burst position modulation and binary phase-shift keying modulation are used to construct the UWB-TX. The synchronization and Viterbi decoder units are used to recover the original data bits and are affected by noise in UWB-RX. The UWB-DTR is synthesized using Xilinx ISE&lt;sup&gt;®&lt;/sup&gt; environment with Verilog hardware description language (HDL) and implemented on Artix-7 field-programmable gate array (FPGA). The UWB-DTR utilizes less than 2% (slices and look-up table/LUTs), operates at 268 MHz, and consumes 91 mW of total power on FPGA. The transceiver achieves a 6.86 Mbps data rate, which meets the IEEE 802.15.4a standard. The UWB-DTR module obtains the bit error rate (BER) of 2×10&lt;sup&gt;-4&lt;/sup&gt; by transmitting 105 data bits. The UWB-DTR module is compared with similar physical layer (PHY) transceivers with improvements in chip area (slices), power, data rate, and BER. &lt;/p&gt;

K‐band CMOS low‐noise amplifier with 180° phase shift function using cascode structure

AbstractIn this study, a K‐band CMOS low‐noise amplifier (LNA) with a 180° phase shift function is presented to reduce the chip area of the beamforming system. The proposed LNA is composed of three stages, and the last stage is designed with a differential cascode structure for 180° phase shift function. The 180° phase shift function was implemented by dividing one cascode transistor into two transistors. As a result, it is possible to equip the 180° phase shift function without an additional chip area. The LNA was designed with a 65‐nm CMOS process to verify the feasibility of the proposed technique. The core size was 0.66 × 0.41 mm2. The measured phase difference between 0° and 180° phase shift modes was approximately 178° in the operating frequency of 22.0 GHz. The measured noise figure and gain were 3.8 and 12.7 dB, respectively.

A Portable Chip-Based NMR Relaxometry System With Arbitrary Phase Control for Point-of-Care Blood Analysis.

In this article, we present a portable NMR relaxometry system optimized for the point-of-care analysis of body liquids such as blood. The presented system is centered on an NMR-on-a-chip transceiver ASIC, a reference frequency generator with arbitrary phase control, and a custom-designed miniaturized NMR magnet with a field strength of 0.29 T and a total weight of 330 g. The NMR-ASIC co-integrates a low-IF receiver, a power amplifier, and a PLL-based frequency synthesizer on a total chip area of 1100 × 900 μm 2. The arbitrary reference frequency generator enables the use of conventional CPMG and inversion sequences, as well as modified water-suppression sequences. Moreover, it is used to implement an automatic frequency lock to correct temperature-induced magnetic field drifts. Proof-of-concept measurements on NMR phantoms and human blood samples show an excellent concentration sensitivity of v[Formula: see text] = 2.2 mM/[Formula: see text]. This very good performance renders the presented system an ideal candidate for the future NMR-based point-of-care detection of biomarkers such as the blood glucose concentration.