(Keynote) Technological Challenges and Emerging Device Architectures for Future Semiconductor Micro and Nanoelectronics

Abstract

Semiconductor technology has known an exponential evolution in the last decades and is fully integrated in our everyday life. According to the Semiconductor Industry association (SIA) the global semiconductor industry sales reaches about US$ 700 billion in 2023, corresponding with a shipment of more than 1.2 trillion components. This necessitates implementation of many novel materials, advanced design concepts and new transistor structures.Increased device performance and reduced power consumption, while maintaining a good manufacturability and yield performance without penalizing the cost/function, are driving microelectronic research towards 3-nm technologies. A large variety of device architectures such as FinFETs, TFETs, negative capacitance, Gate-All-Around, nanowires (NWs), nanosheets (NSs) in both horizontal or vertical configurations, CFET and Forksheet structures are extensively investigated for both logic and analog/RF building blocks enabling System-on-Chip (SoC) applications.In addition to the huge progress achieved in silicon technology, heterogenous integration of Ge and III-V technologies on a silicon platform shows a strong potential, leading towards the on-chip integration of building blocks with different functionality. The fact that both Ge and III-V materials can be selectively grown on Si has strongly triggered the interest in heterogeneous integration.Wide bandgap materials such as GaN offer unique features for RF applications used in base stations for mobile communication, complementing the performance of Si devices suffering from limited output power. These materials can epitaxially be grown on Si substrates. One of the main challenges related to the hetero epitaxy of III-V materials on a Si substrate is the control of extended defects due to the lattice mismatch of the different materials. In recent years, there has been a strong increase in the commercial availability of GaN devices, although for certain applications there is a competition with SiC.Complex and dense SoC applications can be realized by 3D wafer stacking using Through-Silicon-Vias (TSV) for wafer-to-wafer bonding. The 3D integration results in a reduction of the RC product and interconnect length, a smaller form factor and enables vertical partitioning. Main challenges are the TSV process module itself (e.g. Cu via filling, mechanical stress, contamination, keep-out-zone), the wafer thinning and handling and the 3D stacking technology (stacking density, pitch, chip-to-chip interconnect etc.). Very promising results are obtained for monolithic sequential 3D (S3D) processing based on the processing of different tiers on top of each other. Difference can be made between transistor level (n- and pMOS), CMOS level (different standard cells in different tiers) and IP block level for the partitioning. In this way it is e.g. possible to process first CMOS circuits in the Si substrate and then further processing in a III-V layer on top. Benefits are related to an enhanced device density per chip area and a shorter interconnection length. A low cost less scalable tier can be processed on top of an expensive scalable tier as done in the case of logic-memory integration.Major trends in above mentioned process integration approaches are reviewed and technological challenges of some process modules and device structures highlighted.