Design and Implementation of Low Power Time-To-Digital Converter using MGDI Technique

Abstract

This paper introduces a novel Time to Digital Converter (TDC) architecture based on the Modified Gate Diffusion Input (MGDI) technique, which is derived from the well-established GDI method. Through the utilization of MGDI-based logic gates and digital circuitry, this innovative approach leads to a substantial reduction in the number of transistors required for implementation. As a result, it offers significant advantages in terms of circuit area, power consumption, and propagation delay, while simultaneously simplifying the complexity of the overall logic design. The functional blocks within the TDC have been optimized to efficiently process an internal clock frequency of 5MHz. This achievement is realized using cutting-edge 90nm MGDI technology, operating at a supply voltage of 1V. Practical implementation of this design can be carried out seamlessly with Cadence Virtuoso tools in the 90nm technology node. In essence, this research effort represents a promising advancement in the realm of time-to-digital conversion. By harnessing the capabilities of MGDI and its transistor-saving attributes, the proposed TDC not only enhances performance but also addresses critical concerns such as power efficiency and chip area utilization. These advancements make it a compelling choice for applications requiring precise time measurements, while the compatibility with contemporary technology nodes ensures its relevance and applicability in modern integrated circuit design.