A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers

Abstract

This brief proposes a low voltage ultra-low power 10-bit 100-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To overcome the performance degradation due to the signal-related current fluctuation under lower supply voltage, an adaptive-biasing comparator with current self-compensation (CSC) technique is proposed to obtain a constant working current, reducing the minimum supply voltage from 0.7V in conventional ADCs to 0.55V. Since full-scale range shrinks with the supply voltage, voltage undershoot in power rail caused by capacitor digital-to-analog converter (C-DAC) deteriorates effective-number-of-bits (ENOB). Conventional solutions involve enhanced regulators and large decoupling capacitors, which cost remarkable power dissipation and large chip area. This brief presents a pulse-injection undershoot compensation technique which reduces the DAC-related supply fluctuation from a typical 15mV to 1.8mV, and improves the ENOB by 0.4 bit. The prototype was fabricated in TSMC 28nm HPC CMOS technology. The proposed SAR ADC achieves an SNDR of 54.7dB and an SFDR of 68dB with the power consumption of 0.16mW under 0.55V supply voltage, a figure of merit (FoM) of 3.6-fJ/conversion-step is achieved. The chip area of the ADC core is 130μm×225μm.