12-Bit 5 MS/s SAR ADC with Split Type DAC for BLE

Abstract

This paper presents a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) designed for a Bluetooth Low Energy (BLE) application. In order to reduce the number of capacitors in the Capacitor Digital to Analog Converter (CDAC), a split type DAC has been applied in a VCM-based switching scheme. Applying this, the number of the unit capacitors in each CDAC has been reduced by over 14 times. This reduces the area which is dominated by CDAC. Also, the input and reference buffers design specifications are relaxed, and the mismatch is reduced. The conversion speed for this design reaches up to 5 MS/s. The prototype ADC is designed in a 130 nm Complementary Metal-Oxide Semiconductor (CMOS) process. The analog and digital supply voltage ranges for this design are 2.7–5.5 V and 1.1–1.3 V respectively. For 5 MS/s conversion rate, this ADC achieves up to 11.85 and 11.3 effective number of bits (ENOBs), for maximum and minimum supply voltages respectively. The current consumption from a 5 V supply voltage is 560 μA and the Figure of Merit (FOM) is 151 fJ/Conv.step.