A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

Behnam Rikan,Hamed Abbasizadeh,Sang-Yun Kim,Reza Rad,Kang-Yoon Lee,Minjae Lee,Khuram Shehzad,Arash Hejazi,Youngoo Yang,Keum Hwang

doi:10.3390/en11102673

Behnam Rikan, Hamed Abbasizadeh + Show 8 more

Open Access

https://doi.org/10.3390/en11102673

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Abstract

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module, a hybrid-type structure with capacitor and resistor DACs is applied, in which the resistor DAC is shared between channels and determines the seven least significant bits (LSB)s, while the capacitor DAC determines the three most significant bits (MSBs). For the 12-bit operation mode, and to reduce the number of capacitors required in the capacitor DAC, the capacitors of the four channels are shared to determine the five MSBs. A foreground calibration is applied to the capacitor DAC to remedy the gain and offset errors after fabrication. An additional low resistive path is also implemented in the resistor DAC for error correction. The conversion speed for 10- and 12-bit operations reaches up to 1 and 0.5 MS/s, respectively. The prototype ADC is designed in a 180 nm complementary metal-oxide semiconductor (CMOS) process. For 10- and 12-bit operating modes, this ADC module achieves up to 9.71 and 11.76 effective number of bits (ENOBs), respectively.

Highlights

Analog-to-digital converters (ADCs) are applied in almost all system on chip (SoC) designs as the interfaces between the analog and the digital parts
This paper presented a low-area successive approximation register (SAR) ADC module designed for wireless power transfer (WPT) systems
The structure was a four-channel SAR ADC and the resolution of each channel was 10-bit, while the module had the capability of operating as a single 12-bit ADC

Summary

Introduction

Analog-to-digital converters (ADCs) are applied in almost all system on chip (SoC) designs as the interfaces between the analog and the digital parts. Because of the recent design improvements made to successive approximation register (SAR) ADCs, such as resolution and the conversion rate increment, and power consumption reduction, these structures have become more popular, and they are currently widely used in circuit design. To solve the mismatch issue in the CDAC, the unit capacitor sizes should be increased This approach increases the area of these structures. The RDAC is shared between the channels to reduce the required number of the devices and, to reduce the area This structure has a 12-bit operation mode, where the CDACs of all channels are combined to determine the five MSBs. Foreground calibration is applied in the CDACs to remedy offset and gain errors after fabrication.

Block Diagram of the Wireless Power System

Top Block Diagram of the Proposed ADC including Pre–Amplifier and Comparator

Capacitor and Resistor DACs and Timing Diagram

Switching Sequence in CDAC and RDAC

Simulation Result

Conclusions