Abstract
This paper presents the design and implementation of a capacitive digital to analog converter (CDAC) mismatch calibrator used in split successive approximation resistor (SAR) analog to digital converter (ADC) in a 65 nm complementary metal oxide semiconductor (CMOS) process. The calibrator adopts a compensation capacitor connected to the least significant bit (LSB) capacitor array to calibrate the mismatch between the lowest-bit capacitor of the most significant bit (MSB) array and the LSB array. An 11-bit 50-MS/s split SAR ADC using this calibrator was developed. The measurement results show that the calibration process improves the differential nonlinearity (DNL) value from -1.2/+1.9 LSBs to -0.55/+0.75 LSBs and the integral nonlinearity (INL) value from -1.9/+2.12 LSBs to -0.95/+0.99 LSBs. The calibrated ADC achieves a signal to noise and distortion ratio (SNDR) of 58.95 dB near the Nyquist frequency and an effective number of bits (ENOB) of 9.5 bits.
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