A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing

Abstract

Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in high-throughput and high-resolution cases. This paper proposes an analog-oriented RRAM array/read circuits co-design technique to solve the trade-offs between distortion, power consumption, throughput, and chip area. In previous works, the RRAM array is built in a digital mindset that access transistors only serve as switches. Instead, this work investigates a new perspective that utilizes access transistors as common-gate current buffers which reduce the operating current and amplify the output impedance. To further decrease the complexity of peripheral circuits, the idea of In-ADC Computing (IAC) is proposed, which performs shift-add operation together with analog-to-digital conversion. Benefiting from proposed ideas, a pre-trained VGG-8 network based on the CIFAR-10 dataset can be implemented and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit MAC operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still be able to operate in a power-efficient way.