Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor

Abstract

Aggressive voltage scaling to reduce energy consumption in Multicore causes exponential cell failures in SRAM. Last-level-cache (LLC), the major contender of chip area, exhibits highest sensitivity to low voltage parametric failures and limits energy efficiency. To break the energy barrier, exclusive fault protection mechanism is solicited to ensure on-chip data recovery out of the low voltage failures. This work proposes Cache evolution for energy efficiency by protecting cache blocks from SRAM cell failures due to voltage scaling. A set of coherence and reuse aware in-cache selective replication policies are proposed to ensure on-chip data recovery. Reuse likelihood is predicted through a vector optimization technique using Genetic Algorithm (GA). Reuse aware selective invalidation is employed to balance cache load due to replications. A replication aware replacement policy is also developed that victimizes the lowest reusable cache block. The proposed scheme is evaluated in Multi2Sim 5.0 simulation framework with SPEC CPU benchmark programs. Experimental results claim 43.66% and 38.80% reductions in miss rate and 59.10% and 52.73% reductions in vulnerability for integer and floating point benchmarks respectively. Energy reduction of 39.21% is observed for integer and 25.73% is observed for floating point benchmarks. Up to 34.78% and 26.98% power reductions in integer and floating point benchmarks are also observed. The minimum supply voltage of 350 mV is achieved at the cost of 7.05% area overhead and 3% performance drop-off.