Write Power Consumption Research Articles

Hybrid Program Algorithm Enables Significant Reduction in Write Latency and Power Consumption for Multilevel Phase Change Memory

Hybrid Program Algorithm Enables Significant Reduction in Write Latency and Power Consumption for Multilevel Phase Change Memory

Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance

This brief proposes a compact spin-orbit torque magnetic random-access memory (SOT-MRAM) cell structure with high read performance for embedded nonvolatile memory (eNVM) applications. The memory cell is composed of one transistor, two Schottky diodes, two magnetic tunnel junctions (MTJs) and one shared heavy metal (HM) layer, which can be abbreviated as 1T-2D-2MTJ cell. The two MTJs are stacked on the same HM layer for smaller area overhead and configured to be complementary with the magnetization of their pinned layers in the opposite direction to double the read sense margin. The write operation is also simplified since a current through the HM layer changes the resistances of both MTJs simultaneously. The evaluations include the micromagnetic simulation of the SOT device, the analysis of PVT variations for the read operation on bit-cell level, the estimation of bit-cell area and the simulations of performance and power consumption on array level. The results show that the proposed SOT-MRAM improves the performance and reliability of the read operation and achieves 75% (50%) reduction in bit-cell area compared to 4T-2MTJ SOT-MRAM (2T-2MTJ STT-MRAM), 83.0% reduction in write power consumption and 91.1% reduction in write latency compared to 2T-2MTJ STT-MRAM.

A Selective Bit Dropping and Encoding Co-Strategy in Image Processing for Low-Power Design in DRAM and SRAM

A novel and efficient way of image processing is proposed in this paper, which fully exploits the features of DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) as well as the human visual system. The proposed strategy first approximates and encodes the image to effectively reduce the number of bit-‘1’ in the original pixel data, then the processed data is pushed into the off-chip DRAM, and later written into the on-chip SRAM for further computation. Since the storage power consumption of DRAM is proportional to the number of bit-‘1’, while the write power consumption of SRAM is linear relative to the switch probability and the square of the supply voltage, fewer bits-‘1’ in the processed pixel data will decrease the power consumption of DRAM and SRAM, yet accompanied by negligible influence on output quality as our proposed method has the advantages of both approximate computation and error compensation. Thus, a tradeoff is finally achieved between storage power consumption and output quality. In the experimental simulations, 39.8% power reduction for DRAM and 25.9% write power reduction for SRAM have been achieved. Regarding output quality, Discrete Cosine Transform (DCT), quantization, inverse quantization and inverse DCT (IDCT) are employed to process the approximated data. The simulations shows average 3.36 dB losses in Peak-Signal-Noise-Ratio (PSNR). Based on this strategy, an approach of priority-based reduction in supply voltage for insignificant pixel data is introduced to achieve further reduction in power consumption for SRAM. Undoubtedly, a lower supply voltage will increase the probability of read error from SRAM. However, with our proposed approximate coding strategy, the output quality is barely impacted by the lower supply voltage.

A Low-Power, High-Speed Auto-Terminated Write Circuit Architecture With Hybrid MTJ/CMOS Circuits

For the energy waste of write operation in hybrid magnetic tunnel junction (MTJ)/CMOS circuits, an automatic termination write circuit based on 6T write circuit is proposed. The function of eliminating energy waste is achieved by detecting the state of the MTJ in time to detect its writing completion and turn off the writing current. The proposed write circuit reduces the average write power consumption by 47.92% and 76.93% compared to the conventional 4T and 6T write circuits, respectively, and its write speed increases by 20.63% compared to other auto-terminated write circuits. Moreover, Monte Carlo (MC) simulations were performed considering the process errors of CMOS transistors and the actual parameter variations of MTJs to ensure the correct and stable operation of the proposed writing circuit. The proposed writing circuit fully takes into account the randomness and asymmetry of MTJ switching, which is more practical and can work stably in hybrid MTJ/CMOS circuits. The simulation results show that the proposed write circuit has a better performance in terms of low power consumption and speed.

Enhanced spin–orbit torque efficiency with low resistivity in perpendicularly magnetized heterostructures consisting of Si-alloyed β-W layers

Spin-orbit torque (SOT) based magnetization switching is of current technological interest to demonstrate its utilization in nonvolatile embedded memory and logic devices. These devices require perpendicular magnetic anisotropy (PMA) for high bit density, significant SOT efficiency to warrant low power consumption, and external field-free magnetization switching. Above all, materials associated with these devices must be semiconductor fabrication friendly. However, only a few materials and their heterostructures previously explored fulfill the requirements. Here, we propose a W–Si alloy, a widely used material in semiconductor devices, as the spin current-generating layer. First, we investigate the spin Hall conductivity of W–Si alloys by adding Si atoms to the β-W matrix using the first-principles calculations. Then, experimentally, we confirm that the heterostructure consisting of W-Si (4 at%)/CoFeB exhibits PMA, a high damping-like SOT efficiency (∼0.58), and low longitudinal resistivity (∼135 μΩ cm). Furthermore, we estimate ten times smaller write power consumption than the heterostructure based on the pristine β-W. The proposed W–Si/CoFeB heterostructures can withstand post-deposition heat treatment up to 500 °C.

Field-free reliable magnetization switching in a three-terminal perpendicular magnetic tunnel junction via spin-orbit torque, spin-transfer torque, and voltage-controlled magnetic anisotropy

Magnetic field-free switching of a three-terminal perpendicular magnetic tunnel junction driven by spin-orbit torque (SOT) and spin-transfer torque (STT) in the presence of a voltage-controlled magnetic anisotropy (VCMA) effect was investigated using micromagnetic simulation at 300 K. The VCMA effect assists or hinders magnetization switching depending on the polarity of the applied voltage. Thus, the impact of these effects on switching probabilities was evaluated using two write voltage pulses (V SOT, V STT). By optimizing the configuration of these voltage pulses, we demonstrated 100 successful switchings out of 100 trials within 3.2 ns under a limit voltage of 1.0 V. In addition, the write power consumption for SOT-STT writing with optimal pulse configurations was found to be one order of magnitude lower than that of STT-alone writing. We also found that the SOT-STT writing has the great potential in practical use compared with the external magnetic field assisted SOT-writing. Field-free, reliable, and deterministic SOT-STT switching with low power consumption offers significant advantages for embedded memory applications.

Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

This paper explores an ultra-low-power 10T subthreshold SRAM with high stabilities based on 10-nm FinFETs. To prove the superiority of the proposed 10T SRAM's performance, a comparison has been done with existing SRAMs such as the 6T, ST2, DIRP10T, PPN10T, and FC11T at VDD = 0.3 V. The proposed cell offers 2.08X/1.31X/1.03X higher read-stability compared to 6T/ST2/PPN10T due to the use of the read decoupling technique. Writability is increased at least 1.28X by temporarily floating the data node. In the proposed single-ended design, read-bitline does not need to be precharged to VDD to execute read operation, therefore, improving dynamic read power by at least 2.69X. Because of its single-ended nature, the suggested 10T SRAM's dynamic write power consumption is lowered by at least 1.86X. The stacked structure used in the cell core and bitline leakage removed in the read path minimize leakage power by at least 1.50X. Therefore, the proposed design can be an appropriate choice for ultra-low-power applications.

A comprehensive analysis of different 7T SRAM topologies to design a 1R1 W bit interleaving enabled and half select free cell for 32 nm technology node

In this paper, a single-ended, dual port, 1R1 W seven transistor-based static random access memory bit cell is presented. The cell is designed based on a detailed review of various pre-existing 7T cells. All the cells in the paper are evaluated at 32 nm technology and supply voltage of 0.8 V. The static analysis reveals that the hold/read noise margins for the proposed cell are 324 mV each, whereas the write margin is 488 mV. Successful read and write operation for the cell requires a pulse-width of 5 ps and 0.14 ns, respectively. The temperature variation and process corner analysis are used to justify the reliability for the proposed cell. The former analysis yields 0.15 and 0.24 mV/°C variation in the HSNM/RSNM, and WM for the cell. The current ratio for the cell is comparatively higher than other cells. The leakage power consumption for the cell is 256 pW, while its read and write power consumption are 6 µW and 1.9 µW, respectively. Also, the cell is half select disturbance-free and therefore supports bit-interleaving. This ensures the increased reliability for the cell. All the aforementioned merits for the cells are achieved with a minimal layout area of 0.553 µm2.

Tunnel Magnetoresistance Based Passive Resistance Replacement in Hybrid MTJ-CMOS Integration

Previous theoretical and experimental works revealed the novel factors that Magnetic tunnel junction (MTJ) can be integrated into novel hybrid circuits except for memory applications. This paper makes exploitation of tunnel magnetoresistacne based replacement in diminishing layout penalty of on-chip passive component during circuit design and takes sigma-delta analog-to-digital converter (SD-ADC), resistor-based temperature sensor (-55 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula> C <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim 125^{\circ }$</tex-math></inline-formula> C) as two case study where large resistance is needed and restricts the scaling down. Considering the application in MRAM, the mainstream field of MTJ process and dealing with the problems of MRAM in wide temperature write operation, two temperature adaptive write schemes of MRAM are also proposed as the further applications of the proposed MTJ-based temperature sensor. The research of these circuits covers major characteristics of MTJ as the passive component, including area, variation and temperature characteristics. Large CMOS resistance in SD-ADC and bridge transducer in resistor-based temperature sensor are replaced by MTJ-based resistors. Simulation results reveal that the layout area of passive resistors in resistor-capacitor (RC) integrator was greatly reduced by the tunnel magnetoresistacne based replacement, specifically by 94.52% in comparison with fully 28nm CMOS design or 94.13% for wide temperature use. As for other figures of merit (FoM), Effective Numbers of Bits (ENOB) is improved by 0.06 bit along with higher thermal stability, and Signal-to-Noise Ratio (SNR) is decreased by 1.1 dB as design trade-off. In addition, the MTJ based bridge transducer in resistor-based temperature sensor can reduce the resistance layout area by over 90% with better linearity comparing with general CMOS resistor-based temperature sensor designs. Based on the MTJ-based temperature sensor, the two different adaptive write circuits help reduce write power consumption and delay of MRAM respectively for wide temperature use.

Novel low‐power and stable memory cell design using hybrid CMOS and MTJ

SummaryMemory is an essential component of any VLSI data storage system. Because of the shrinking of CMOS processing nodes, power consumption in conventional memory (SRAM and DRAM) increases. Traditional memory technologies also suffer several additional difficulties, such as limited scalability, low reliability, short data retention time, low durability, increased space, and latency, among others. As a result, new device technologies are critical for developing low‐power, high‐performance memory devices. Among the numerous developing nonvolatile (NV) memory technologies available today, STT‐MRAM is regarded as one of the most appealing and promising NV memory technologies for overcoming the limitations of traditional memories. STT‐MRAM is more efficient, quicker, NV, highly scalable, and readily integrated with CMOS technology. Because of the scalability of technology nodes below 45 nm, traditional STT‐MRAM cells have several difficulties, including high write power consumption, destructive read and write operation, prolonged write time, and so on. To address the issues associated with the writing operation of STT‐MRAM cells, this article presented an optimum STT‐MRAM cell design based on PMA‐MTJ. The write failure mitigation strategies are utilized to increase the proposed cell's write stability. A comparative analysis between conventional STT‐MRAM cell and the proposed cell is performed by concerning the write power consumption, write delay, and write stability. The experimental results indicate the performance superiority of the proposed cell architecture.

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

A Systematic Assessment of W-Doped CoFeB Single Free Layers for Low Power STT-MRAM Applications

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) technology is considered to be the most promising nonvolatile memory (NVM) solution for high-speed and low power applications. Dual MgO-based composite free layers (FL) have driven the development of STT-MRAMs over the past decade, achieving data retention of 10 years at the cost of higher write power consumption. In addition, the need for tunnel magnetoresistance (TMR)-based read schemes limits the flexibility in materials beyond the typical CoFeB/MgO interfaces. In this study, we propose a novel spacerless FL stack comprised of CoFeB alloyed with heavy metals such as tungsten (W) which allows effective modulation of the magnet properties (Ms, Hk) while retaining compatibility with MgO layers. The addition of W results favours a delayed crystallization process, in turn enabling higher thermal budgets up to 180 min at 400 °C. The presence of tungsten reduces the total FL magnetization (Ms) but simultaneously increasing its temperature dependence, thus, enabling a dynamic write current reduction of ~15% at 2 ns pulse widths. Reliable operation is demonstrated with a WER of 1 ppm and endurance &gt;1010 cycles. These results pave the way for alternative designs of STT-MRAMs for low power electronics.

Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption

Tunnel field-effect transistors (TFETs) have become a potential candidate for replacing traditional MOSFETs in ultralow-power applications, in future. However, the forward p-i-n current of the TFET can seriously deteriorate the performance of the static random-access memory (SRAM) circuit. This brief proposes a half-select disturb-free 10T TFET SRAM cell with cascode isolation transistors. The proposed 10T SRAM cell can avoid the forward p-i-n current, drastically decreasing its leakage power consumption. At a supply voltage of 0.6 V, the leakage power consumption of the proposed 10T TFET SRAM cell is approximately four orders of magnitude lower than those of the outward-facing access transistor 6T (O_6T)/7T and the Schmitt–Trigger 10T (ST_10T) SRAM cells; the write power consumption is approximately 97% and 98% lower than those of the O_6T/7T/ST_10T and the combinational access 10T (CA_10T) SRAM cells, respectively. Moreover, the 10T SRAM cell exhibits 20% and 57% higher read static noise margin(RSNM) than those of the O_6T/7T and ST_10T cells, 115% and 411% higher write static noise margin(WSNM) than those of O_6T/7T and CA_10T, respectively, 20% higher hold static noise(HSNM) than those of O_6T/7T/ST_10T cells, and 89.8% lesser write delay than that of CA_10T at VDD = 0.6V, indicating that the proposed 10T SRAM cell has great potential for ultra-low power applications.

Investigation of 7T SRAM Cell for IoT based devices

Internet of Thing (IoT) based devices require the design of ultra-low power Static Random Access Memory (SRAM) to sustain the long battery life. In present work, for execution different types of SRAM cell methodologies Cadence Virtuoso tool is used and all considered methodologies read and write operations have been supervised out. These SRAM cell methodologies various parameters also have been calculated, there are read static noise margin (RSNM), write static noise margin (WSNM), read delay, write delay, read power and write power. For low read, write power dissemination and faster read and write working new 7T SRAM cell methodology is proposed. It has been recognized that new 7T SRAM cell methodology as collated to 6T to 9T SRAM cell methodologies read power consumption reduced by 1.60* to 4*. New 7T SRAM cell methodology as collated to traditional 6T, 8T and 9T SRAM cell write power consumption is decreased by 2.3* to 2.6*. It is also noticed that as collated to 6T, 8T and 9T SRAM cell methodology that new 7T SRAM read delay suppressed by 2.40* to 2.60* and its write delay is also suppressed by 3.80* to 99*. As collate to 6T to 9T SRAM cell methodologies write operation robustness of new 7T SRAM cell is 3.0* to 6.5* perform in better way. New 7T SRAM cell has the tradeoff that its read operation robustness is 6* to 14* lesser as collate to 6T, 8T and 9T SRAM cell methodologies. Due to low power consumption and less delay new 7T SRAM cell methodology is suitable for Internet of things (IOT) based devices.

A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future Directions

Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we first revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.

Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM

The reverse bias current of the tunneling field-effect transistor (TFET) could cause serious damage to static random-access memory (SRAM) circuit performance. To address this issue, a novel reverse bias current eliminated, read-separated, and write-enhanced TFET 12T SRAM bitcell is proposed for ultra-low power applications in this brief. It can prevent reverse bias currents, increase the hold/read static noise margin (H/RSNM) and dramatically decrease the static power consumption. The static power consumption of the proposed bitcell is reduced by four orders of magnitude compared with that of the 7T bitcell, demonstrating its great potential for ultra-low power applications. At a supply voltage of 0.6 V, the H/RSNM of the proposed bitcell is 25% larger than that of the 7T bitcell. It also includes a write assist circuit, thus increasing its write static noise margin (WSNM) and considerably decreasing its write power consumption. The WSNM of the proposed bitcell is more than twice that of the 7T bitcell, and is 60% larger than that of the combinational access bitcell. In addition, the write power consumption of the proposed bitcell is reduced by 95% compared with that of the combinational access bitcell at a supply voltage of 0.6 V. In terms of layout, the area of the proposed 12T bitcell is 92% larger than that of the 7T bitcell, but is 6% smaller than the area of the combinational access bitcell.

A highly stable reliable SRAM cell design for low power applications

The growth in demand for power-efficient neural network accelerators has generated an intense demand for low power static random access memory (SRAM). In this context, a power-efficient transmission gate based 9-Transistor (TG9T) SRAM bitcell has been proposed in this work. In order to assess the relative performance of the proposed design in terms of major design metrics, it has been juxtaposed with contemporaneous designs such as the feedback-cutting 7T, fully differential 8T (FD8T) and single-ended disturb free 9T (SEDF9T) bitcells, while the reliability of such SRAM designs when subjected to process variations has also been analyzed. In terms of read stability (RSNM), the TG9T shows 2.87×/3.36× higher RSNM and 2.90×/2.67× narrower spread in RSNM, respectively, as compared to 7T/FD8T. In addition, it also exhibits 1.4×/6.55× higher write ability (WSNM) and 1.01×/5.05×/1.06× narrower spread in WSNM when compared with FD8T/SEDF9T and FD8T/SEDF9T/7T respectively. Moreover, a 1.15×/1.06× narrower spread in read delay (TRA) and 1.54×/1.38× narrower spread in read current (IREAD) are also exhibited by the proposed design in comparison with 7T/FD8T. The reliable nature of TG9T is indicated by the narrower spread in read stability, write ability, read delay and read current. Furthermore, in comparison with 7T/FD8T, TG9T consumes 2.92×/1.04× lower hold power. Additionally, the proposed cell shows 10.80×/17.81× lower write power consumption and 1.43×/18.37× lower read power consumption when compared to that of SEDF9T/FD8T and 7T/FD8T respectively. Amongst all SRAM bitcells used for comparison, the proposed bitcell yields the lowest VDD,min. The TG9T cell achieves all the aforementioned improvements at the cost of 1.22×/1.34× longer TWA and 1.93×/1.93× longer TRA when compared with 7T/SEDF9T and 7T/FD8T, respectively, at a supply voltage of 0.7 V.

Impact of variations of threshold voltage and hold voltage of threshold switching selectors in 1S1R crossbar array**Project supported by the MOST of China (Grant No. 2016YFA0201801), the Beijing Advanced Innovation Center for Future Chip (ICFC), Beijing Municipal Science and Technology Project (Grant No. D161100001716002), and the National Natural Science Foundation of China (Grant Nos. 61674089, 61674087, 61674092, 61076115, and 61774012),

The impact of the variations of threshold voltage (Vth) and hold voltage (Vhold) of threshold switching (TS) selector in 1S1R crossbar array is investigated. Based on ON/OFF state I–V curves measurements from a large number of Ag-filament TS selectors, Vth and Vhold are extracted and their variations distribution expressions are obtained, which are then employed to evaluate the impact on read process and write process in 32 × 32 1S1R crossbar array under different bias schemes. The results indicate that Vth and Vhold variations of TS selector can lead to degradation of 1S1R array performance parameters, such as minimum read/write voltage, bit error rate (BER), and power consumption. For the read process, a small Vhold variation not only results in the minimum read voltage increasing but it also leads to serious degradation of BER. As the standard deviation of Vhold and Vth increases, the BER and the power consumption of 1S1R crossbar array under 1/2 bias, 1/3 bias, and floating scheme degrade, and the case under 1/2 bias tends to be more serious compared with other two schemes. For the write process, the minimum write voltage also increases with the variation of Vhold from small to large value. A slight increase of Vth standard deviation not only decreases write power efficiency markedly but also increases write power consumption. These results have reference significance to understand the voltage variation impacts and design of selector properly.

Write Energy Reduction for PCM via Pumping Efficiency Improvement

The emerging Phase Change Memory (PCM) is considered to be a promising candidate to replace DRAM as the next generation main memory due to its higher scalability and lower leakage power. However, the high write power consumption has become a major challenge in adopting PCM as main memory. In addition to the fact that writing to PCM cells requires high write current and voltage, current loss in the charge pumps also contributes a large percentage of high power consumption. The pumping efficiency of a PCM chip is a concave function of the write current. Leveraging the characteristics of the concave function, the overall pumping efficiency can be improved if the write current is uniform. In this article, we propose a peak-to-average (PTA) write scheme, which smooths the write current fluctuation by regrouping write units. In particular, we calculate the current requirements for each write unit by their values when they are evicted from the last level cache (LLC). When the write units are waiting in the memory controller, we regroup the write units by LLC-assisted PTA to reach the current-uniform goal. Experimental results show that LLC-assisted PTA achieved 13.4% of overall energy saving compared to the baseline.

Reliable high-yield CNTFET-based 9T SRAM operating near threshold voltage region

We propose a reliable high-yield nine-carbon-nanotube field-effect transistor (9-CNTFET) static random-access memory (SRAM) cell using shared bit line and half-select-free techniques. The proposed SRAM cell operates near the threshold voltage of 325 mV. The proposed cell was also tested and verified under process variation, exhibiting stable write and read operations. Due to the reduced leakage current of the proposed cell, the power consumption is significantly decreased by 4.98-fold compared with the conventional six-transistor (6T) cell. Although the use of a CNT array increases the probability of functionality of the CNTFET, it occupies 1 % more area. Due to its high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio, shortest node, shared bit line, and high-efficiency read and write ports, the read and write access time of the proposed nine-transistor (9T) SRAM cell is improved by 43 and 98 %, respectively, compared with the conventional 6T device. When using the low-feature-size CNTFET device in a new 9T SRAM cell, the area overhead is reduced to 32.9 % compared with previously published 9T SRAM cells. The proposed cell operates with minimum supply voltage near the threshold voltage region, reducing the read and write power consumption per bit by 1.2- and 1.8-fold, respectively, compared with existing 9T SRAM cells.