Investigation of 7T SRAM Cell for IoT based devices

Abstract

Internet of Thing (IoT) based devices require the design of ultra-low power Static Random Access Memory (SRAM) to sustain the long battery life. In present work, for execution different types of SRAM cell methodologies Cadence Virtuoso tool is used and all considered methodologies read and write operations have been supervised out. These SRAM cell methodologies various parameters also have been calculated, there are read static noise margin (RSNM), write static noise margin (WSNM), read delay, write delay, read power and write power. For low read, write power dissemination and faster read and write working new 7T SRAM cell methodology is proposed. It has been recognized that new 7T SRAM cell methodology as collated to 6T to 9T SRAM cell methodologies read power consumption reduced by 1.60* to 4*. New 7T SRAM cell methodology as collated to traditional 6T, 8T and 9T SRAM cell write power consumption is decreased by 2.3* to 2.6*. It is also noticed that as collated to 6T, 8T and 9T SRAM cell methodology that new 7T SRAM read delay suppressed by 2.40* to 2.60* and its write delay is also suppressed by 3.80* to 99*. As collate to 6T to 9T SRAM cell methodologies write operation robustness of new 7T SRAM cell is 3.0* to 6.5* perform in better way. New 7T SRAM cell has the tradeoff that its read operation robustness is 6* to 14* lesser as collate to 6T, 8T and 9T SRAM cell methodologies. Due to low power consumption and less delay new 7T SRAM cell methodology is suitable for Internet of things (IOT) based devices.