A Robust SRAM cell for high performance Register File

Abstract

Today robust and high performance SRAM (static random access memory) cells are highly demanded in industries. The research work discusses the read static noise margin (RSNM) and write static noise margin (WSNM). The proposed NTl2T (Noise tolerant NTl2T) SRAM cell topology consists of distinct read and write access transistors. This eliminates the conflicting design requirements for access transistors which arise in conventional 6T SRAM cell design. It will also increase the read as well as write stability. Two read and one write port enhance the performance of bit cell. The proposed cell eliminates the charge controversy during read and write operation, therefore its VTC curve is similar to ideal VTC curve. In addition, the bit cell shows enhancement in average write & read power dissipation. The simulation results shows that the proposed NTl2T SRAM bit cell is more noise tolerant than conventional6T, 8T & 10T SRAM cells. The area overhead is l.97x & l.67x more than conventional 6T & 8T SRAM cell respectively. The compared result of analytical WSNM with SPICE simulation give a little variation of 6.66% for 6T, 6.82% for 8T, 6.98% for 10T and 7.46% for proposed NTl2T. An improvement of l.32x Il.46x Il.l2x in RSNM and l.33x Il.24x /Ll 1×in WSNM is observed when proposed NTl2T is compared with 6T, 8T and 10T SRAM cells respectively. The maj or challenge is to design high stability SRAM design. The result of the proposed cell has been compared with 32nm HSPICE technology with VDD @ 0.9 V. Further the proposed design is validated by implementation through Register File.