A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology

Abstract

Data stability, performance and leakage currents are the few important issues of Static Random Access Memory (SRAM) due to scaling down the technology. We revisited these issues by making a comparative study of N-Controlled SRAM cell (NC-SRAM) and PMOS pass transistor SRAM cell (PP-SRAM) with conventional 6T SRAM cell. We observe decrease in Static Noise Margin (SNM) of NC-SRAM and PP-SRAM cells with 6T SRAM cell in hold mode by 60.09% and 0.22% at temperature (T) = 25°C, 63.25% and 3.34% at T = 50°C, 63.82% and 3.37% at T = 100°C respectively. For our transistors sizing we obtain a degradation in write operation of NC-SRAM cell by 7.31% compare to 6T SRAM cell, While it is unchanged in case of PP-SRAM cell. Significant reduction in total leakage power is obtained for NC and PP-SRAM cells compared to 6T SRAM cell by 77.06% and 47.42% at T = 25°C, 76.89% and 48.98% at T = 50°C, 76.87% and 50.94% at T = 100°C respectively, which is due to the gate and sub-threshold leakage currents. We also design a 16 bit memory array of 6T, NC and PP SRAM cells. There is a reduction in total leakage power for 16 bit array of NC and PP-SRAM cells by 69.86 %, 50.75 % respectively compared to the 16 bit array of 6T SRAM cell. All the simulations are performed by Cadence Virtuoso (version IC 6.1.6.500.1) tool using gpdk 45nm CMOS process technology.