Design and analysis of memory array using 45 nm nanotechnology of 7T SRAM cell and assess it performance

Abstract

The transistor mismatch can be described as two closely placed identical transistors have important differences in their electrical parameters as threshold voltage, body factor and current factor and make integrated circuit design and fabrication less predictable and controllable. Stability of a static random access memory (SRAM) is defined through its ability to retain the data at low-VDD. It is seriously affected by increased variability of transistor mismatch and decreased supply voltage and therefore becomes a major limitation of overall performance of low-voltage SRAM in nanometer CMOS process. The stability limitation is addressed through the design of a seven-transistor (7T) SRAM cell and of which the stability analysis and comparison with the conventional 6T SRAM cell is presented. This research also presents two 8-bit SRAM designs implemented by 6T and 7T SRAM cells respectively. The robustness of both designs is tested and verified through transistor mismatch and environmental process variations. Results obtained show 7T SRAM outperform 6T SRAM when stability is of a major concern.