A highly reliable NBTI Resilient 6T SRAM cell

Abstract

In this work, a highly reliable six-transistor (6T) Static Random Access Memory (SRAM) cell is proposed. The proposed SRAM cell is resilient to Negative Bias Temperature Instability (NBTI), since, PMOS pull-up transistors are replaced by their counterpart NMOS pull-up transistors. We compared the different parameters and performance indices (static noise margin and energy per operation) of the proposed SRAM cell with the standard 6T and loadless 4T SRAM cells. In order to achieve full logic level in the proposed SRAM cell, we studied the effect of PMOS as access transistors and compared with the loadless 4T SRAM cells with and without NBTI effect. It is observed that the proposed PMOS access transistors based SRAM cell yield better reliability (120% improvement in read SNM) with marginal increase in energy per operation as compared to NMOS access transistors. The leakage current of the proposed SRAM cell is 57× less than the 4T SRAM cell. The proposed SRAM cell design has positive impact of NBTI stress and yields significant improvement in the SRAM cell reliability as compared to its counterpart standard 6T SRAM cell.