Reverse Bias Current Eliminated, Read-Separated, and Write-Enhanced Tunnel FET SRAM

Abstract

The reverse bias current of the tunneling field-effect transistor (TFET) could cause serious damage to static random-access memory (SRAM) circuit performance. To address this issue, a novel reverse bias current eliminated, read-separated, and write-enhanced TFET 12T SRAM bitcell is proposed for ultra-low power applications in this brief. It can prevent reverse bias currents, increase the hold/read static noise margin (H/RSNM) and dramatically decrease the static power consumption. The static power consumption of the proposed bitcell is reduced by four orders of magnitude compared with that of the 7T bitcell, demonstrating its great potential for ultra-low power applications. At a supply voltage of 0.6 V, the H/RSNM of the proposed bitcell is 25% larger than that of the 7T bitcell. It also includes a write assist circuit, thus increasing its write static noise margin (WSNM) and considerably decreasing its write power consumption. The WSNM of the proposed bitcell is more than twice that of the 7T bitcell, and is 60% larger than that of the combinational access bitcell. In addition, the write power consumption of the proposed bitcell is reduced by 95% compared with that of the combinational access bitcell at a supply voltage of 0.6 V. In terms of layout, the area of the proposed 12T bitcell is 92% larger than that of the 7T bitcell, but is 6% smaller than the area of the combinational access bitcell.