Design and Analysis of Low-Power SRAM

Abstract

The Static Random Access Memory (SRAM) is an integral part of memory architectures. With growing technology and scaling factor, static power consumption needs to be minimized. Therefore, an SRAM cell desires the new techniques and architecture, which can operate at very low sub-threshold voltage. In this paper, PN-based 10T SRAM cell (PPN10T) and transmission-based 8T (TG8T) have been analyzed and proposed a new 8T SRAM cell (P8T) to overwhelm the problems faced by conventional 6T SRAM (C6T) cell. The selection of W/L ratio and bit-line leakage problem has been significantly resolved for low-power SRAM design. Moreover, C6T, PPN10, TG8T cells and P10T has been compared for different performance parameters such as hold noise margin, read static noise margin (RSNM), write static noise margin (WSNM), read delay, write delay, Iread/Ileak ratio, hold power dissipation and dynamic power dissipation.