A Robust 13T Single Ended Schmitt Trigger Based SRAM Cell

Abstract

Static Random Access Memory (SRAM) cells are widely used in many applications, such as cache and registers in various electronic circuits. Recently, due to internet of things (IoT) the memory devices need low voltage operation. The SRAM cell has already been implemented using six transistors in ultra-deep submicron technology to lower the power consumption. However, the conventional 6T SRAM cells implemented at lower voltages are suffering from the lower tolerance against the process, voltage, and temperature (PVT) variations. The Schmitt trigger (ST) based SRAM cell is used to overcome such variations. In this paper, a robust 13T-ST based SRAM has been implemented. Further, the performance of the 13T SRAM cell is compared with the conventional 6T SRAM cell. The comparison is made by varying the supply voltage from O.5V to 1V. Further, we have obtained the access time, power, and static noise margin (SNM) for both designs. Simulation results show that the 13T Schmitt trigger based SRAM has O.41x write ‘1’ access time, 2.31x write SNM, 2.23x read SNM, 1.1x hold SNM, 0.80x leakage power as compared with conventional 6T SRAM at 700mV.