Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption

Abstract

Tunnel field-effect transistors (TFETs) have become a potential candidate for replacing traditional MOSFETs in ultralow-power applications, in future. However, the forward p-i-n current of the TFET can seriously deteriorate the performance of the static random-access memory (SRAM) circuit. This brief proposes a half-select disturb-free 10T TFET SRAM cell with cascode isolation transistors. The proposed 10T SRAM cell can avoid the forward p-i-n current, drastically decreasing its leakage power consumption. At a supply voltage of 0.6 V, the leakage power consumption of the proposed 10T TFET SRAM cell is approximately four orders of magnitude lower than those of the outward-facing access transistor 6T (O_6T)/7T and the Schmitt–Trigger 10T (ST_10T) SRAM cells; the write power consumption is approximately 97% and 98% lower than those of the O_6T/7T/ST_10T and the combinational access 10T (CA_10T) SRAM cells, respectively. Moreover, the 10T SRAM cell exhibits 20% and 57% higher read static noise margin(RSNM) than those of the O_6T/7T and ST_10T cells, 115% and 411% higher write static noise margin(WSNM) than those of O_6T/7T and CA_10T, respectively, 20% higher hold static noise(HSNM) than those of O_6T/7T/ST_10T cells, and 89.8% lesser write delay than that of CA_10T at VDD = 0.6V, indicating that the proposed 10T SRAM cell has great potential for ultra-low power applications.