A Low-Power, High-Speed Auto-Terminated Write Circuit Architecture With Hybrid MTJ/CMOS Circuits

Abstract

For the energy waste of write operation in hybrid magnetic tunnel junction (MTJ)/CMOS circuits, an automatic termination write circuit based on 6T write circuit is proposed. The function of eliminating energy waste is achieved by detecting the state of the MTJ in time to detect its writing completion and turn off the writing current. The proposed write circuit reduces the average write power consumption by 47.92% and 76.93% compared to the conventional 4T and 6T write circuits, respectively, and its write speed increases by 20.63% compared to other auto-terminated write circuits. Moreover, Monte Carlo (MC) simulations were performed considering the process errors of CMOS transistors and the actual parameter variations of MTJs to ensure the correct and stable operation of the proposed writing circuit. The proposed writing circuit fully takes into account the randomness and asymmetry of MTJ switching, which is more practical and can work stably in hybrid MTJ/CMOS circuits. The simulation results show that the proposed write circuit has a better performance in terms of low power consumption and speed.