A highly stable reliable SRAM cell design for low power applications

Abstract

The growth in demand for power-efficient neural network accelerators has generated an intense demand for low power static random access memory (SRAM). In this context, a power-efficient transmission gate based 9-Transistor (TG9T) SRAM bitcell has been proposed in this work. In order to assess the relative performance of the proposed design in terms of major design metrics, it has been juxtaposed with contemporaneous designs such as the feedback-cutting 7T, fully differential 8T (FD8T) and single-ended disturb free 9T (SEDF9T) bitcells, while the reliability of such SRAM designs when subjected to process variations has also been analyzed. In terms of read stability (RSNM), the TG9T shows 2.87×/3.36× higher RSNM and 2.90×/2.67× narrower spread in RSNM, respectively, as compared to 7T/FD8T. In addition, it also exhibits 1.4×/6.55× higher write ability (WSNM) and 1.01×/5.05×/1.06× narrower spread in WSNM when compared with FD8T/SEDF9T and FD8T/SEDF9T/7T respectively. Moreover, a 1.15×/1.06× narrower spread in read delay (TRA) and 1.54×/1.38× narrower spread in read current (IREAD) are also exhibited by the proposed design in comparison with 7T/FD8T. The reliable nature of TG9T is indicated by the narrower spread in read stability, write ability, read delay and read current. Furthermore, in comparison with 7T/FD8T, TG9T consumes 2.92×/1.04× lower hold power. Additionally, the proposed cell shows 10.80×/17.81× lower write power consumption and 1.43×/18.37× lower read power consumption when compared to that of SEDF9T/FD8T and 7T/FD8T respectively. Amongst all SRAM bitcells used for comparison, the proposed bitcell yields the lowest VDD,min. The TG9T cell achieves all the aforementioned improvements at the cost of 1.22×/1.34× longer TWA and 1.93×/1.93× longer TRA when compared with 7T/SEDF9T and 7T/FD8T, respectively, at a supply voltage of 0.7 V.