Implementation of an Efficient SRAM for Ultra-Low Voltage Application Based on ST for Better Read Stability and Write Ability

Abstract

Operation of standard 6T static random access memory (SRAM) cells at sub or near threshold voltages is unfeasible, predominantly due to degraded static noise margins (SNM) and poor robustness. We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read- stability as well as better write-ability compared to the standard 6T bitcell. In this paper we are going to propose a new SRAM bitcell for the purpose of read stability and write ability by using 90nm technology , and less power consumption, less area than the existing Schmitt trigger1 based SRAM. Design and simulations were done using DSCH and Microwind. Index Terms: read stability, write ability, Schmitt trigger. I. Introduction PORTABLE electronic devices have extremely low power requirement to maximize the battery lifetime. Various device-/circuit-architectural-level techniques have been implemented to minimize the power consumption. Supply voltage scaling has significant impact on the overall power dissipation.With the supply voltage reduction, the dynamic power reduces quadratically while the leakage power reduces linearly (to the first order). However, as the supply voltage is reduced, the sensitivity of circuit parameters to process variations increases. This limits the circuit operation in the low-voltage regime, particularly for SRAM bitcells employing Minimum-sizedtransistor. These minimum geometry transistors are vulnerable to interdie as well as intradie process variations. Intradie process variations include random dopant fluctuation (RDF) and line edge roughness (LER). This may result in the threshold voltage mismatch between the adjacent transistors in a memory bitcell, resulting in asymmetrical characteristics. The combined effect of the lower supply voltage along with the increased process variations may lead to and increased memory failures such as read-failure, hold-failure, write- failure, access-time failure. Moreover, it is predicted that embedded cache memories, which are expected to occupy a significant portion of the total die area, will be more prone to failures with scaling.