Design of a Low-Power One-Sided Schmitt-Trigger Based 13T SRAM Bitcell

Abstract

This study describes the design of a novel 13-transistor (13T) Static Random Access Memory (SRAM) bitcell that employs a single bitline design with isolated transistors used for write and read operation. The bitcell incorporates Schmitt- Trigger based inverters, resulting in a considerable rise in cell's static noise margin. A power gating approach is also used to increase the bitcell's write capabilities, resulting in reduced power consumption during write operations. The proposed bitcell was designed using a 0.18μm technology in Cadence Virtuoso Software. The various performance parameters like stability, Power Consumption, Delay and Leakage power are compared against the conventional 6T SRAM bitcell. Overall, the proposed 13T SRAM bitcell outperforms the conventional 6T SRAM cell in every aspect.