Process variation tolerant 9T SRAM bitcell design

Abstract

In this paper, a nine-transistor (9T) Static Random Access Memory (SRAM) bitcell for the low voltage and energy constraint applications is proposed. It is well known that in sub-threshold regime, reliability and process variations are the main design challenges, and standard six-transistor (6T) SRAM bitcell fails to operate in sub-V TH . The proposed design has better read stability and improved process variation tolerant as compared to standard 6T SRAM at low voltage. Simulation results based on 32nm technology node shows that there is 37% improvement in the read stability as compared to standard 6T SRAM bitcell. The proposed design also address the conflicting read and write requirements, therefore, one can optimize the read static noise margin (SNM), write noise margin and write speed for a particular application by selecting the bitcell ratios for read and write operations.