Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

Abstract

This paper explores an ultra-low-power 10T subthreshold SRAM with high stabilities based on 10-nm FinFETs. To prove the superiority of the proposed 10T SRAM's performance, a comparison has been done with existing SRAMs such as the 6T, ST2, DIRP10T, PPN10T, and FC11T at VDD = 0.3 V. The proposed cell offers 2.08X/1.31X/1.03X higher read-stability compared to 6T/ST2/PPN10T due to the use of the read decoupling technique. Writability is increased at least 1.28X by temporarily floating the data node. In the proposed single-ended design, read-bitline does not need to be precharged to VDD to execute read operation, therefore, improving dynamic read power by at least 2.69X. Because of its single-ended nature, the suggested 10T SRAM's dynamic write power consumption is lowered by at least 1.86X. The stacked structure used in the cell core and bitline leakage removed in the read path minimize leakage power by at least 1.50X. Therefore, the proposed design can be an appropriate choice for ultra-low-power applications.