Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell

Abstract

Scaling of MOS technology creates new challenges to the SRAM circuit design, mainly leakage power and stability. A new seven transistor SRAM (7T) is proposed in this paper which eliminates the stability issues, reliable write and has a reduced cell area. Leakage current in proposed 7T SRAM cell without Super cut-off word lines is almost same as in 6T SRAM cell and proposed 7T SRAM cell with super cut-off word lines is reduced by 26% of leakage power present in 6T SRAM cell. Compared to the conventional 7T SRAM cell, the proposed cell has reduced write delay, read power consumption and write power consumption. Read delay is reduced by almost half of the standard 7T SRAM. The proposed 7T SRAM is compared with existing 6T, 7T, 8T and 9T SRAM cells in 60nm technology. The Overall performance of proposed 7T is best among the standard 6T, 7T, 8T, 9T.