A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance

Abstract

Static Random Access Memory cell has been under immense design updation recently with an aim to enhance its performance, to withstand the device level process variations and simultaneously support low power applications. SRAMs are used as memory reserve in digital processing systems due to their high speed performance. But, standard 6T SRAM bit-cells suffer from sizing issue which further results in a trade-off between the write ability and read stability of the cell. In this paper, we propose a 20 nm FinFET based 10 transistor (10T) SRAM bit-cell design based on single ended sensing. The read stability has increased significantly in the proposed SRAM design in comparison to standard 6T SRAM bit-cell since it has a separate bit line discharging path for decoupling the data storage-nodes completely from the read path. Data cognizant word lines and PMOSs as power gating transistors are used to enhance the write ability. Hence, it gives better read and write static noise margin (RSNM and WSNM) as compared to standard 6T SRAM cell. In comparison to previous 10T SRAM bit-cells, the proposed bit-cell design shows enhanced read-write operations. The simulations have been performed using Predictive Technology Model (PTM) files for 20 nm FinFET on HSPICE. The supply voltage has been kept at 0.9 V for the proposed bit-cell. The area of proposed bit-cell has been found to increase by 1.55 times in comparison to standard 6T SRAM cell and has been found to be similar to that of previous 10T SRAM bit-cell.